STLC1502 データシートの表示（PDF） - STMicroelectronics

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コンポーネント説明

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STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

STLC1502

Pin

44

45

46

52

53

188

Miscellaneous

47

Pin Name

pxtalout

edmiclk

testarmclk

selarmfreq

rstn

clkout

bootsel_treqa

118

hpisel

Memory I/F (shared signals)

125, 126, 127, 129,

130, 131, 133, 134,

135, 136, 137, 138,

140, 141

add[0..13]

62, 63, 64, 65, 66, 69,

70, 71, 72, 73, 74, 75,

77, 78, 79, 81, 82, 84,

85, 86, 88, 89, 91, 92,

93, 95, 96, 98, 99,

100, 102, 103

data[0..31]

2, 3, 4, 5

wenbsn[0..3]

6

oen

ESM (specific controls)

142, 144, 145, 146, add[14..21]

148, 149, 150, 152

6/81

Pin Description/Note

8.192 MHz crystal feedback

SDRAM feedback clock (input)

ARM clock in bypass mode

Selects ARM PII Vco frequency

Asynchronous Master Reset Input

25MHz master clock out

Pin

Drive

8mA

4mA

Pin

Type

O

I/O

I

I

I

O

Boot selection: Select internal [1]

I

or external [0] booting ROM. If

proper test configuration has been

selected, then signal assumes Tic

request A functionality

Select between HPI[1] or

I

GPIO_KBD IF [0]

Memory address bus.

4mA

O

For Dynamic RAM, they are the

whole address, whereas for static,

they are the LSBits addresses. At

power up or hardware reset all

address values are 0

Memory data bus, to exchange

8mA

I/O

data between memory controller

and external memories

Write byte enable for external

8mA

O

static RAM or byte strobe for

dynamic external RAM

Output enable for static/dynamic 8mA

O

external RAM. At power up or

hardware reset, the signal will be

asserted if the external booting

(bootsel = ‘1’) has been selected

Memory address bus’ MSBits.

4mA

O

They complete the ESM

addressability. A total of 4Mbyte

external (FLASH/SRAM) address

space is addressed by the

STLC1502 device. At the first fetch

of instruction after power_up or

hardware reset, all address values

are ‘0’

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