VSC9112 データシートの表示（PDF） - Vitesse Semiconductor

部品番号

コンポーネント説明

メーカー

VSC9112

STS-48c Physical Layer Packet/ATM Over SONET/SDH Device

Vitesse Semiconductor 

Datasheet

VSC9112

VITESSE

SEMICONDUCTOR CORPORATION

STS-48c Physical Layer

Packet/ATM Over SONET/SDH Device

• The SPE Transparent Mode is provided to allow the Tx FIFO content to be passed directly into the SPE

payload without further processing.

Transmit Path Overhead Processor (TPOP)

• The H1 and H2 pointer byte values are programmable to support both SONET and SDH. Several pointer

functions are provided for diagnostics purposes. The remaining 47 H1 and H2 bytes are programmable.

• The Path BIP-8 is computed and placed in the B3 byte of the current frame. It is possible to insert B3

errors for diagnostic purposes.

• The number of Path BIP-8 errors detected in the Receive Path Overhead Processor (RPOP) is backre-

ported as Path REI in the G1 byte. Both individual and block mode backreporting for G1 are supported.

• It is possible to enable/disable RDI-P insertion for each of the following alarms: LOS, LOF, AIS-L, AIS-

P, LOP-P, TIM-P, UNEQ-P, LCD-P and PLM-P. Both the latest and earlier definitions of RDI-P are sup-

ported.

• The Path Signal Label (C2) byte value is programmable.

• The Path Trace (J1) byte value is programmable.

• The F2, H4, Z3, Z4, and Z5 bytes are programmable.

Transmit Line Overhead Processor (TLOP)

• It is possible to insert programmable sets of K1 and K2 bytes into the outgoing data stream.

• RDI-L can be automatically inserted during the detection of an LOS, LOF, or AIS-L alarm in the receive

data stream.

• The Line BIP-384 code is computed and placed in the B2 bytes of the current frame. It is possible to

insert B2 errors for diagnostics purposes.

• The number of Line BIP-384 errors detected in the Receive Line Overhead Processor (RLOP) is backre-

ported as Line REI in the M1 byte. Up to 255 errors can be backreported per frame in individual mode.

Both individual and block mode backreporting for M1 are supported. It is possible to insert M1 error

indications for diagnostics purposes.

• The Synchronization Status value inserted in the S1 byte is programmable.

• Bytes input to the special purpose ports of the Transmit Overhead Access Port (TOAP) can be inserted

into the D4-D12, E2, S1, K1 and K2 bytes of the outgoing Line overhead.

• All bytes in the line overhead that are reserved for national or future international standardization use can

be overwritten with 0x00.

• The H1, H2, and H3 bytes from the Transmit Overhead Access Port (TOAP) can be inserted into the H1,

H2, and H3 overhead bytes, or applied as an error mask to the H1, H2, and H3 overhead bytes.

Transmit Section Overhead Processor (TSOP)

G52210-0, Rev. 4.3

3/30/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 7

Share Link: