SMJ28F010B データシートの表示（PDF） - Austin Semiconductor

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SMJ28F010B

131072 BY 8-BIT FLASH MEMORY

Austin Semiconductor 

SMJ28F010B

131072 BY 8-BIT

FLASH MEMORY

SGMS738 – APRIL 1998

flow charts (continued)

Start

Preprogram

All Bytes = 00h No

?

Yes

Address = 00h

Program All

Bytes to 00h

VCC = 5 V ± 10%, VPP = 12 V ± 5%

X=1

Setup

Write Set-Up-Erase Command

Write-Erase Command

Wait = 10 ms

Write Erase-Verify Command

X=X+1

Interactive

Mode

Bus

Operation

Command

Comments

Entire memory must = 00h

before erasure

Use fast-write

programming algorithm

Initialize addresses

Standby

Wait for VPP to ramp to

VPPH (see Note A)

Initialize pulse count

Write

Set-Up-

Erase

Data = 20h

Write

Erase

Data = 20h

Increment

Address

Wait = 6 µs

Read

Fail

and Verify

Byte

Pass

No

X = 1000?

Yes

No

Last

Address?

Yes

Write Read Command

Apply VPPL

Apply VPPL Power

Down

Device Passed

Device Failed

Standby

Wait = 10 ms

Write

Erase-

Verify

Addr = Byte to verify;

Data = A0h; ends the erase

operation

Standby

Wait = 6 µs

Read

Read byte to verify erasure;

compare output to FFh

Write

Read

Standby

Data = 00h; resets register

for read operations

Wait for VPP to ramp to

VPPL (see Note B)

NOTES: A. Refer to the recommended operating conditions for the value of VPPH.

B. Refer to the recommended operating conditions for the value of VPPL.

Figure 2. Flash-Erase Flow Chart

10

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