SMJ28F010B データシートの表示（PDF） - Austin Semiconductor

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SMJ28F010B

131072 BY 8-BIT FLASH MEMORY

Austin Semiconductor 

SMJ28F010B

131072 BY 8-BIT

FLASH MEMORY

SGMS738 – APRIL 1998

programming and erasure

In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to

a logic 0. Then the entire chip is erased. At this point, the bits, which are now logic 1s, can be programmed

accordingly. See the fast-write and fast-erase algorithms for further details.

command register

The command register controls the program and erase functions of the SMJ28F010B. The algorithm-selection

mode can be activated using the command register in addition to the previously described method. When VPP

is high, the contents of the command register and the function being performed can be changed. The command

register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse,

while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two

commands must be executed to invoke either operation. The command register is inhibited when VCC is below

the erase / write lockout voltage, VLKO .

power-supply considerations

Each device must have a 0.1-µF ceramic capacitor connected between VCC and VSS to suppress circuit noise.

Changes in current drain on VPP require it to have a bypass capacitor as well. Printed-circuit traces for both

power supplies should be appropriate to handle the current demand.

command definitions

The commands include read, algorithm-selection mode, set-up-erase, erase, erase-verify, set-up-program,

program, program-verify, and reset. Table 3 lists the command definitions with the required bus cycles.

Table 3. Command Definitions

COMMAND

REQUIRED

BUS

CYCLES

FIRST BUS CYCLE

OPERATION† ADDRESS

DATA

SECOND BUS CYCLE

OPERATION† ADDRESS DATA

Read

1

Write

X

00h

Read

RA

RD

Algorithm-Selection Mode

3

Write

X

90h

Read

0000h

89h

0001h

B4h

Set-Up-Erase / Erase

2

Write

X

20h

Write

X

20h

Erase-Verify

2

Write

EA

A0h

Read

X

EVD

Set-Up-Program / Program

2

Write

X

40h

Write

PA

PD

Program-Verify

2

Write

X

C0h

Read

X

PVD

Reset

2

Write

X

FFh

Write

Legend:

EA

Address of memory location to be read during erase verify

RA

Address of memory location to be read

PA

Address of memory location to be programmed. Address is latched on the falling edge of W.

RD

Data read from location RA during the read operation

EVD Data read from location EA during erase verify

PD

Data to be programmed at location PA. Data is latched on the rising edge of W.

PVD Data read from location PA during program verify

† Modes of operation are defined in Table 1.

X

FFh

read command

Memory contents can be accessed while VPP is high or low. When VPP is high, writing 00h into the command

register invokes the read operation. When the device is powered up, the default contents of the command

register are 00h and the read operation is enabled. The read operation remains enabled until a different

command is written to the command register.

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