SMJ28F010B データシートの表示（PDF） - Austin Semiconductor

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SMJ28F010B

131072 BY 8-BIT FLASH MEMORY

Austin Semiconductor 

SMJ28F010B

131072 BY 8-BIT

FLASH MEMORY

SGMS738 – APRIL 1998

fast-write algorithm

Figure 1 shows the process flow for programming the SMJ28F010B. The fast-write algorithm programs in a

nominal time of two seconds.

fast-erase algorithm

Figure 2 shows the process flow for erasing the SMJ28F010B using the fast-erase algorithm. The memory array

must be completely programmed (using the fast-write algorithm) before erasure begins. Erasure typically

occurs in one second.

parallel erasure

Several devices can be erased in parallel, reducing total erase time. Since the rate at which each flash memory

can erase differs, every device must be verified separately after each erase pulse. After a given device has been

successfully erased, the erase command should not be reissued to this device. All devices that complete

erasure should be masked until the parallel erasure process is finished (see Figure 3).

Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command

(00h) to the device when the others receive a set-up-erase or erase command, and disconnecting the device

from all electrical signals with relays or other types of switches.

flow charts

Figure 1, Figure 2, and Figure 3 are flow charts showing the fast-write algorithm, the fast-erase algorithm, and

the parallel-erase flow.

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