GS832218C-133I データシートの表示（PDF） - Giga Semiconductor

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GS832218C-133I

2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs

Giga Semiconductor 

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36 119-Bump BGA Pin Description

Pin Location

Symbol

P4, N4

A0, A1

R2, C3, B3, C2, A2, A3, A5, A6, T3,

T5, R6, C5, B5, C6, B6, B2

An

T4, T6

An

T2

NC

T2, T6, T4

An

K7, L7, N7, P7, K6, L6, M6, N6

H7, G7, E7, D7, H6, G6, F6, E6

H1, G1, E1, D1, H2, G2, F2, E2

K1, L1, N1, P1, K2, L2, M2, N2

DQA1–DQA8

DQB1–DQB8

DQC1–DQC8

DQD1–DQD8

P6, D6, D2, P2

DQA9, DQB9,

DQC9, DQD9

L5, G5, G3, L3

BA, BB, BC, BD

P7, N6, L6, K7, H6, G7, F6, E7, D6 DQA1–DQA9

D1, E2, G2, H1, K2, L1, M2, N1, P2 DQB1–DQB9

L5, G3

BA, BB

B1, C1, R1, T1, U6, B7, C7, J3, J5,

R7

NC

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

NC

G5, L3

K4

CK

M4

BW

H4

GW

E4

E1

F4

G

G4

ADV

A4, B4

ADSP, ADSC

T7

ZZ

R5

FT

R3

LBO

Type

I

I

—

I

I/O

I/O

I

I/O

I

—

—

I

I

I

I

I

I

I

I

I

I

D4

ZQ

I

L4

SCD

I

U2

TMS

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Input (x36 Version)

No Connect (x36 Version)

Address Input (x18 Version)

Data Input and Output pins. (x36 Version)

Data Input and Output pins. (x36 Version)

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

Data Input and Output pins (x18 Version)

Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

No Connect

No Connect (x18 Version)

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],

High = High Impedance [Low Drive])

Single Cycle Deselect/Dual Cyle Deselect Mode Control

Scan Test Mode Select

Rev: 1.00 10/2001

9/44

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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