AD7450BRM データシートの表示（PDF） - Analog Devices
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AD7450BRM Datasheet PDF : 24 Pages
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PRELIMINARY TECHNICAL DATA
AD7450
Parameter
POWER REQUIREMENTS
VDD
IDD8,10
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
A Version1 B Version1 Units
Test Conditions/Comments
3/5
3/5
Vmin/max Range: 3 V ± 10%; 5 V ± 5%
1
1
mA typ
VDD =3 V/5 V. SCLK On or Off
2.6
2.6
mA max VDD = 5 V. fSAMPLE=1MSPS
2
2
mA max
VDD = 3 V. fSAMPLE=833kSPS
1
1
µA max SCLK On or Off
13
13
mW max VDD =5 V. fSAMPLE=1MSPS
6
6
mW max VDD =3 V. fSAMPLE=833kSPS
5
5
µW max VDD =5 V. SCLK On or Off
3
3
µW max VDD =3 V. SCLK On or Off
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C.
2See ‘Terminology’ section.
3Common Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figure 8.
4Because the input span of VIN+ and VIN- are both VREF, and they are 180° out of phase, the differential voltage is 2 x VREF.
5The reference is functional from 100mV and for 5V supplies it can range up to TBDV (see ‘Reference Section’).
6The reference is functional from 100mV and for 3V supplies it can range up to 2.2V (see ‘Reference Section’).
7Sample tested @ +25°C to ensure compliance.
8See POWER VERSUS THROUGHPUT RATE section.
8TCONVERT + TQUIET (See ‘Serial Interface Section’)
10Measured with a midscale DC input.
Specifications subject to change without notice.
AD7450 - TIMING SPECIFICATIONS 1,2
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
Parameter +3V
+5V
Units
Description
fSCLK 4
tCONVERT
tQUIET
t1
t2
t
5
3
t
5
4
t5
t6
t7
t
6
8
t
P
O
W
E
R
-
U
7
P
10
15
16 x tSCLK
1.07
50
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
45
TBD
10
18
16 x tSCLK
0.88
50
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
45
TBD
kHz min
MHz max
µs max
tSCLK = 1/fSCLK
SCLK = 15MHz, 18MHz
ns min Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of CS
ns min Minimum CS Pulsewidth
ns min CS falling Edge to SCLK Falling Edge Setup Time
ns max Delay from CS Falling Edge Until SDATA 3-State Disabled
ns max Data Access Time After SCLK Falling Edge
ns min SCLK High Pulse Width
ns min SCLK Low Pulse Width
ns min SCLK Edge to Data Valid Hold Time
ns min SCLK Falling Edge to SDATA 3-State Enabled
ns max SCLK Falling Edge to SDATA 3-State Enabled
µs max Power-Up Time from Full Power-Down
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2See Figure 1 and the “Serial Interface” section.
3Common Mode Voltage.
4Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD = 3 V.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7 See ‘Power-up Time’ Section.
Specifications subject to change without notice.
REV. PrJ
–3–
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