L4969MD データシートの表示（PDF） - STMicroelectronics

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L4969MD

SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER

STMicroelectronics 

L4969

1.2 Power-Up, Initialization and Sleep mode transitions

The following state-diagram illustrates the possible mode transitions inside the device.

As a prerequisite, a SPI-connection to the uC with the correct CRC-algorythms is required.

During the debug phase the NRES line can be forced high externally (connect to V1) to deactivate the startup

failure mechanis keeping V1 will alive.

Figure 3.

After POR, V1 up or externally forced reset

through low NRES, the STARTUP STATE is

entered

The forced sleep mode is left upon wakeup through either CAN or edge on

WAKE. Applying a permanent wakeup (i.e. both CAN-lines dominant) pre-

vents V1 from being turned off (can be used during System debugging)

V1 Low

NRES Low

WAKEUP

STARTUP

V1 active

V2, V3, CAN off

WAKEUP

Forcing NRES high externally, fail will not be incremented (Emulation)

t=320ms

t=1ms

STARTUP

FAILURE

RESET low

(fail ++)

fail = 7

FORCED SLEEP

V1 off

No Reset

WDC-ACK

A missing ACK within 320ms will

initiate a STARTUP FAILURE

phase (RESET low).

WDC-FAIL

WDC-ACK

&

If no WDC-ACK is received within

seven retrials the voltage regulator

V1 will be turned off by entering the

FORCED SLEEP state.

Dependig on the value from the last

WDEN SET

WDC-ACK, another one has to be

The Window supervision can temporarily be de-

Writing to the WDC-

register (WDC-ACK)

the NORMAL STATE is

written within the specified time frame

(SWDC[1:0]). A failure will activate

the STARTUP STATE

entered.

NORMAL MODE WDC-ACK

WINDOW WDC t=tWIN2

WINDOW

WATCHDOG

ACTIVE

WDC-OK REFRESH

activated for the time programmed during the

last WDC-ACK (WDT[3:0]). Upon rewriting

(WDC-ACK) or expiry of the timer, the NORMAL

STATE is reentered.

WDEN SET

TIMER

ACTIVE

(restart by double

WDC-ACK & WDEN)

WND SET

TIMEOUT | WDC-ACK

DISAR

SET

If during the last WDC-ACK WND has been set (after releasing

write lock, see description of Watchdog Control Register) the Win-

dow watchdog is deactivated, and no uC supervision is active.

Here the timer can be used to

generate time events (i.e.

wakeup uC from stop)

NORMAL MODE

WINDOW WDC

DISABLED

WDEN SET

TIMEOUT | WDC-ACK

TIMER

ACTIVE

(restart by double

WDC-ACK & WDEN)

WAKEUP

DISAR

SET

WAKEUP

&V1_UV

Programmed

SLEEP

V1 OFF

No Reset

Setting DISAR (see Voltage Regulator Control Register) Voltage regulator V1 is

turned off, and the output voltage is decreasing depending on the external load

and blocking capacitor.

Note, that during this transition no Reset will be generated (due to Debugmode).

Upon wakeup howewer NRES will be pulled low, if V1was below the programma-

ble reset threshold (V1_UV).

WAKEUP&V1_UV

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