DS2141AN データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2141AN

T1 Controller

Dallas Semiconductor -> Maxim Integrated 

DS2141A

RCR2: RECEIVE CONTROL REGISTER 2 (2Ch)

(MSB)

RCS

RZBTSI

RSDW

RSM

RSIO

RD4YM

FSBE

(LSB)

BPVCRS

SYMBOL

RCS

POSITION

RCR2.7

RZBTSI

RCR2.6

RSDW

RCR2.5

RSM

RSIO

RCR2.4

RCR2.3

RD4YM

RCR2.2

FSBE

RCR2.1

BPVCRS

RCR2.0

NAME AND DESCRIPTION

Receive Code Select.

0=idle code (7F Hex).

1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex).

Receive Side ZBTSI Enable.

0=ZBTSI disabled.

1=ZBTSI enabled.

RSYNC Double–Wide.

0=do not pulse double–wide in signaling frames.

1=do pulse double–wide in signaling frames.

(note: this bit must be set to 0 when RCR2.4 = 1 or when RCR2.3 = 1).

RSYNC Mode Select.

0=frame mode (see the timing in Section 13).

1=multiframe mode (see the timing in Section 13).

RSYNC I/O Select.

0=RSYNC is an output.

1=RSYNC is an input (only valid if elastic store enabled).

(note: this bit must be set to 0 when CCR1.2 = 0).

Receive Side D4 Yellow Alarm Select.

0=0 in bit 2 of all channels.

1=a 1 in the S–bit position of frame 12.

Fs–Bit Error Report Enable.

0=do not report bit errors in the Fs–bit position in FECR.

1=report bit errors in the Fs–bit position in FECR.

BPVCRS Function Select.

0=counts bipolar violations.

1=counts ESF error events (CRC6 OR ’ed with RLOS).

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