3933 データシートの表示（PDF） - Allegro MicroSystems
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3933 Datasheet PDF : 12 Pages
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3933
THREE-PHASE POWER
MOSFET CONTROLLER
Terminal Descriptions
Terminal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
PGND
RESET
GLC
SC
GHC
CC
GLB
SB
GHB
CB
GLA
SA
GHA
CA
VCCOUT
LCAP
FAULT
MODE
VBB
H1
H3
H2
DIR
BRAKE
BRKCAP
BRKSEL
PWM
RC
SENSE
REF
DEAD
AGND
RESET — A logic input used to enable the device, internally
pulled up to VLCAP (+5 V). A logic HIGH will disable the
device and force all gate drivers to 0 V, coasting the motor. A
logic LOW allows the gate drive to follow commutation logic.
This input overrides BRAKE.
GLA/GLB/GLC — Low-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 50 ns.
SA/SB/SC — Directly connected to the motor, these terminals
sense the voltages switched across the load. These terminals
are also connected to the negative side of the bootstrap capaci-
tors and are the negative supply connections for the floating
high-side drive.
GHA/GHB/GHC — High-side, gate-drive outputs for external
NMOS drivers. External series-gate resistors (as close as
possible to the NMOS gate) can be used to control the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. Each output is designed and
specified to drive a 1000 pF load with a rise time of 100 ns.
CA/CB/CC — High-side connections for the bootstrap capaci-
tors, positive supply for high-side gate drive. The bootstrap
capacitor is charged to approximately VCCOUT when the
associated output SA/SB/SC terminal is low. When the output
swings high, the voltage on this terminal rises with the output to
provide the boosted gate voltage needed for n-channel power
FETs.
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