SAA7780 データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

SAA7780

ThunderBird Q3D™ PCI Audio Accelerator

Philips Electronics 

Philips Semiconductors

Product Specification

ThunderBird Q3D PCI Audio

Accelerator

SAA7780

BIT Width Device Access Rules

Device

Data

Cycle Types Width

Comments

PCI Configuration

Registers

Config Read Any

Config Write

Game Port

AC’97 Codec

DMA Interface

Sound Blaster

Registers

Host/DSP Interface

Virtual Registers

Host/DSP Interface

I/O Read

I/O Write

I/O Read

I/O Write

I/O R/W

I/O Read

I/O Write

I/O Read

I/O Write

Mem Read

I/O Read

I/O Write

8

16

Any

8

8,16

Any

8,16

MPU401 Registers I/O Read

8

I/O Write

16650 UART

I/O Read

8

I/O Write

Follow PCI addressing rules, otherwise assert a target abort.

Note that configuration registers, no matter where they are,

are accessed by configuration cycles only. Note that the PLL

will only allow 8 bit configuration accesses, the Virtual

Registers TBLBASE registers are 32 bit access only, and the

VRCFG is 16 bit access only.

Any other access will result in a target abort.

For PIO type accesses, only 16 bit I/O cycles are allowed,

other wise a target abort will result.

Any other access will result in a target abort.

Word accesses must be word aligned.

Follow PCI addressing rules.

Usually, only 16 bit accesses will be used to download and

access the DSP. Byte wide are also allowed for DSP

configuration accesses. Word access must be on word

boundaries.

Any other access will result in a target abort.

Any other access will result in a target abort.

The PCI interface consists of three major blocks, the PCI master interface, the PCI slave interface and the PCI

datapath. The PCI master interface contains the master state machine, the master control logic, and the PM bus

arbiter. The PCI slave interface contains the target state machine, the target control logic and configuration register

headers. The PCI datapath is the de-multiplexing logic for the address, data and byte enable data paths for the PS and

PM busses. The PM and PS busses are described in detail in the SAA7780 Internal Busses section. Partitioning of

these PCI blocks is done in this manner to reduce block inter-connectivity and to provide an interface between the three

major sections of the PCI interface.

PCI Master Interface

The SAA7780 PCI master interface performs the memory read and write cycles initiated by the DMA or Virtual

Registers blocks. The major components of the PCI master interface are the master state machine, the PM bus arbiter

and the master control logic. Each of the functional blocks will be discussed in detail.

PCI Master State Machine

This block performs the handshaking between the PCI interface and the PM internal bus. The PCI master will perform

1999 Sep 30

28

Share Link: