CXD2492R データシートの表示（PDF） - Sony Semiconductor
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CXD2492R Datasheet PDF : 35 Pages
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CXD2492R
Serial interface clock internal loading characteristics (2)
VD
HD
Enlarged view
Example: During frame mode
VD
0.2VDDd
HD
SEN
ts1
0.8VDDd
th1
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD.
Symbol
ts1
th1
(Within the recommended operating conditions)
Definition
Min. Typ. Max. Unit
SEN setup time, activated by the falling edge of VD
0
ns
SEN hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2492R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2492R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
Output signal
0.8VDDd
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
tpdPULSE Output signal delay, activated by the rising edge of SEN
Min. Typ. Max. Unit
5
100 ns
– 10 –
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