CXD2452R データシートの表示（PDF） - Sony Semiconductor
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CXD2452R Datasheet PDF : 28 Pages
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CXD2452R
Pin Description
Pin
No.
Symbol
1 3MCK
2 Vss1
3 WEN
4 ID
5 TEST
6 VDD1
7 XCLPOB
8 VDD2
9 RG
10 Vss2
11 Vss3
12 H1
13 H2
14 VDD3
15 XCLPDM
16 VDD4
17 XSHP
18 XSHD
19 XRS
20 Vss4
21 PBLK
22 1/2MCK
23 3/2MCK
24 VDD5
25 RST
26 VDD6
27 SSI
28 SSK
29 SEN
30 EBCKSM
31 FRO
I/O
Description
I Internal main clock. (2340fH)
— GND
O
Memory write timing.
Stop control possible using the serial interface data.
O
Vertical direction line identification pulse output.
Stop control possible using the serial interface data.
I IC test pin; normally fixed to GND. (With pull-down resistor)
— 3.3V power supply. (Power supply for common logic block)
O
CCD optical black signal clamp pulse output.
Stop control possible using the serial interface data.
— 3.3V power supply. (Power supply for RG)
O CCD reset gate pulse output. (780fH)
— GND
— GND
O CCD horizontal register drive clock output. (780fH)
O CCD horizontal register drive clock output. (780fH)
— 3.3V power supply. (Power supply for H1/H2)
O Pulse output for dummy bit block clamp .
— 3.3V power supply. (Power supply for CDS system)
O Precharge level sample-and-hold pulse output. (780fH)
O Data level sample-and-hold pulse output. (780fH)
O Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH)
— GND
O Pulse output for horizontal and vertical blanking interval pulse cleaning.
O
Horizontal direction pixel identification pulse output.
Stop control possible using the serial interface data.
—
System clock output for signal processing IC (1170fH).
Stop control possible using the serial interface data.
— 3.3V power supply. (Power supply for common logic block)
I
Internal system reset input. High: Normal status, Low: Reset status
Always input one reset pulse after power-on.
— 3.3V power supply. (Power supply for common logic block)
I Serial interface data input for internal mode settings.
I Serial interface clock input for internal mode settings.
I Serial interface strobe input for internal mode settings.
I
CHKSUM enable. (With pull-down resistor)
High: Sum check invalid, Low: Sum check valid
O
Vertical sync signal output.
Stop control possible using the serial interface data.
–3–
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