CXD2450R データシートの表示（PDF） - Sony Semiconductor
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CXD2450R Datasheet PDF : 30 Pages
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CXD2450R
Description of Operation
Pulses output from the CXD2450R are controlled by the RST and DSGAT pins and by the serial interface data
shown below. The details of control by the serial interface data and a description of operation are as follows.
SSI
SSK
SEN
00 01 02 03 04 05 06 07 08 09 10 11 58 59 60 61 62 63 64 65 66 67 68 69 70 71
The CXD2450R basically loads and reflects the serial interface data sent in the above format in the readout
portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which V2a and
V2b take the ternary level.
There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these
data are distinguished by referring to the former as control data and the latter as adjustment data.
An example of the initialization data for the CXD2450R control data is shown below. This data is based on the
Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin
initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the
3/2MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71
CHKSUM is valid.
MSB
LSB
D71 D70 D69 D68 D67 D66 D65 D64 D63 D62 D61 D60 D59 D58 D57 D56
10
10
1
101
0
00
0
0010
MSB
LSB
D55 D54 D53 D52 D51 D50 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40
11
01
0
000
0
00
0
0000
MSB
LSB
D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24
00
00
0
000
0
00
0
0000
MSB
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08
00
00
0
000
0
00
0
0000
MSB
LSB
D07 D06 D05 D04 D03 D02 D01 D00
10
00
0
001
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the
system configuration or for other reasons, the data considered most appropriate at that time should be set as
the initialization data.
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