STLC60134S データシートの表示（PDF） - STMicroelectronics

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STLC60134S

TOSCA™ INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT

STMicroelectronics 

STLC60134S

Table 15. Phase characteristics

Description

Total TX filter group delay

Total TX filter group delay distortion

Value/Unit

<50µs @ 34.5kHz < f < 138kHz

<20µs @ 34.5kHz < f < 138kHz

Note: The total ATU-R TX path (including DAC) group delay distortion is 16µs (i.e. = 15µs + 1µs of DAC)

Figure 10. SC Filter Mask for ATU-CRX and ATU-R TX

AMPLITUTDE

0dB

+/-1dB

20dB

30

D98TL363

138 250

KHz

Table 16. D/A Convertor (A current steering architecture is used).

Description

Numbers of bits:

Minimum resolution of the D/A convertors

Linearity error of the A/D convertor

Full scale input range:

Sampling rate:

Maximum group delay:

Maximum group delay distortion:

Value/Unit

12bits

11bits

<1LSB (out of 12bits)

1 Vpdif ±5%

8.832MHz (or 4.416MHz in compatible mode)

<3µs

<1µs

Linearity of ATU-C TX

Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and

each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the pre-driver for the case of a total AGC = 0dB.

Table 17. Linearity of ATU-C TX

f1 (0.5Vpd)

f2 (0.5Vpd)

S/IM3 (AGC = 0dB)

300kHz

200kHz

59.5dB @ 100kHz

53.5dB @ 400kHz

43.5dB @ 700kHz

42.5dB @ 800kHz

500kHz

400kHz

59.5dB @ 300kHz

48.0dB @ 600kHz

700kHz

600kHz

48.0dB @ 500kHz

42.5dB @ 800kHz

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