STLC60134S データシートの表示（PDF） - STMicroelectronics

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STLC60134S

TOSCA™ INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT

STMicroelectronics 

STLC60134S

Figure 4. ATU-C END Block Diagram.

POTS

LINE

Zo=100

LP

POTS FILTER

2:1

HP POTS FILTER

RXT1

RXT2

R

R

RXP(0:1)

12.5

2R

12.5

2R

GRX

LPF

RXN(0:1)

0..31dB

LNA

35.328MHz

XTRAL

DRIVER

LP138KHz

SC2

MASTER CLOCK

35.328MHz

NIBBLES 17.664MHz

WORD 8.832/4.416MHz

RXn

8.832MS/s

12-bit A/D

4

4.416MS/s

CONVERTER

CTRLIN

LTNT=1

RESETN

TO

STLC60135

GTX

LINE

DRIVER

HPF

TXP

TXN

-15..0dB

PD

ATU-R END: BLOCK DIAGRAM

The ATU-R side block diagram is equal to the

ATU-C side block diagram with the following dif-

ferences:

- The transformer ratio is 1:1

- Termination resistors are 50Ω for 100Ω lines.

An LP filter may be used on the TX path to re-

Figure 5. ATU-R END Block Diagram.

LP 1.1MHz

HC2

4

12-bit D/A

CONVERTER

TXn

8.832MS/s

4.416MS/s

D98TL357mod

duce DMT sidelobes and out of band noise influ-

ence on the receiver. On the RX path, a HP filter

must be used in order to reduce the echo signal

level and to avoid saturation of the input stage of

the receiver.

The POTS filter is used in both directions to re-

duce crosstalk between ADSL signals and POTS

speech and signalling. Low pass POTS filter can

be very simple for Lite - ADSL application

POTS

LINE

Zo=100

LP

POTS FILTER

1:1

HP POTS FILTER

RXT1

RXT2

R

R

RXP(0:1)

50

2R

50

GRX

HPF

RXN(0:1)

2R

VCXOUT

VCODAC

0. .31dB

LNA

35.328

MHz

XTAL

DRIVER

LP 1.1MHz

HC2

4

12- bit A/D

CONVERTER

MASTER CLOCK

35.328MHz

NIBBLES 17.664MHz

WORD 8.832/4.416MHz

RXn

8.832MS/s

4.416MS/s

CTRLIN

LTNT=0

RESETN

TO

STLC60135

6/22

GTX

LI NE

DRIVER

TXP

LPF

TXN

-15..0dB

PD

LP 138KHz

SC2

4

12-bit D/A

CONVERTER

TXn

8.832MS/s

4.416MS/s

D98TL358mod

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