ADG467(Rev0) データシートの表示（PDF） - Analog Devices
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ADG467 Datasheet PDF : 8 Pages
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ADG466/ADG467
CIRCUIT INFORMATION
where ∆V is due to I × R voltage drop across the channels of the
Figure 7 below shows a simplified schematic of a channel
MOS devices (see Figure 9). As can be seen from Figure 9, the
protector circuit. The circuit is made up of four MOS transis-
current during fault condition is determined by the load on the
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path but is used to connect the
output (i.e., VCLAMP/RL). However, if the supplies are off, the
fault current is limited to the nano-ampere level.
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and so increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
Figures 8, 10 and 11 show the operating conditions of the signal
path transistors during various fault conditions. Figure 8 shows
how the channel protectors operate when a positive overvoltage
is applied to the channel protector.
have a resistance of 60 Ω typ. The channel protectors are very
low power devices, and even under fault conditions the supply
VDD – VTN*
(+13.5V)
current is limited to sub micro-ampere levels. All transistors are
POSITIVE
NMOS
PMOS
NMOS
OBSOLETE dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel
protectors. For an explanation, see “Trench Isolation” section.
VSS
NMOS
PMOS
NMOS
VDD
PMOS
VSS
VDD
Figure 7. The Channel Protector Circuit
Overvoltage Protection
When a fault condition occurs on the input of a channel
OVERVOLTAGE
(+20V)
SATURATED
NON-
SATURATED
VDD (+15V)
VSS (–15V)
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
NON-
SATURATED
VDD (+15V)
Figure 8. Positive Overvoltage on the Channel Protector
The first NMOS transistor goes into a saturated mode of
operation as the voltage on its Drain exceeds the Gate voltage
(VDD) – the threshold voltage (VTN). This situation is shown in
Figure 9. The potential at the source of the NMOS device is
equal to VDD – VTN. The other MOS devices are in a nonsaturated
mode of operations.
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of opera-
tion as the drain voltage exceeds VSS – VTP. See Figure 10 be-
low. As in the case of the positive overvoltage, the other MOS
protector, the voltage on the input has exceeded some threshold devices are nonsaturated.
voltage set by the supply rail voltages. The threshold voltages
are related to the supply rails as follows. For a positive overvolt-
age, the threshold voltage is given by VDD – VT where VTN is the
threshold voltage of the NMOS transistor (1.5 V typ). In the
case of a negative overvoltage the threshold voltage is given by
VSS – VTP where VTP is the threshold voltage of the PMOS
device (2 V typ). If the input voltage exceeds these threshold
voltages, the output of the channel protector (no load) is
clamped at these threshold voltages. However, the channel
protector output will clamp at a voltage that is inside these
NEGATIVE
OVERVOLTAGE
(–20V)
VSS – VTP*
(–13V)
NEGATIVE
OVERVOLTAGE
(–20V)
NMOS
PMOS
NON-
SATURATED
SATURATED
VDD (+15V)
VSS (–15V)
*VTP = PMOS THRESHOLD VOLTAGE (–2V)
NMOS
NON-
SATURATED
VDD (+15V)
thresholds if the output is loaded. For example with an output
load of 1 kΩ, VDD = 15 V and a positive overvoltage. The output
will clamp at VDD – VTN – ∆V = 15 V – 1.5 V – 0.6 V = 12.9 V
Figure 10. Negative Overvoltage on the Channel Protector
VD
VG
VS
∆V
(+20V)
(VDD =15V)
(+13.5V)
OVERVOLTAGE
OPERATION
(SATURATED)
N+
N CHANNEL N +
N+
EFFECTIVE
SPACE CHARGE
REGION
VT = 1.5V P –
(VG – VT = 13.5V)
PMOS
NMOS
NONSATURATED
OPERATION
IOUT
VCLAMP
RL
Figure 9. Positive Overvoltages Operation of the Channel Protector
REV. 0
–5–
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