ADG467(Rev0) データシートの表示（PDF） - Analog Devices
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ADG467 Datasheet PDF : 8 Pages
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ADG466/ADG467
The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
diode clamping (see “Applications Information”). When VDD
and VSS equal 0 V, all transistors are off and the current is
limited to subnano-ampere levels (see Figure 11).
channel protector will not exceed the threshold voltages set by
the supplies (see “Circuit Information”) when there is an
overvoltage on the input. When the input voltage does not
exceed these threshold voltages, the channel protector behaves
like a series resistor (60 Ω typ). The resistance of the channel
protector does vary slightly with operating conditions (see
“Typical Performance Graphs”).
The power sequencing protection is afforded by the fact that
(0V)
when the supplies to the channel protector are not connected,
POSITIVE OR
NEGATIVE
OVERVOLTAGE
NMOS
PMOS
NMOS
the channel protector becomes a high resistance device. Under
this condition all transistors in the channel protector are off and
the only currents that flow are leakage currents, which are at the
OFF
OFF
OFF
µA level.
OBSOLETE VDD (0V)
VSS (0V)
VDD (0V)
Figure 11. Channel Protector Supplies Equal to Zero Volts
TRENCH ISOLATION
The MOS devices that make up the channel protector are
isolated from each other by an oxide layer (trench) (see Figure
12). When the NMOS and PMOS devices are not electrically
isolated from each other, there exists the possibility of “latch-
up” caused by parasitic junctions between CMOS transistors.
Latch-up is caused when P-N junctions that are normally
reverse biased become forward biased, causing large currents to
flow, which can be destructive.
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation, the N and P wells of the
CMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
EDGE
CONNECTOR
+5V
–5V
VDD
VSS
ANALOG IN
–2.5V TO +2.5V
LOGIC
LOGIC
GND
ADG466
ADC
CONTROL
LOGIC
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With Trench Isolation, this diode is removed; the
result is a latch-up proof circuit.
Figure 13. Overvoltage and Power Supply Sequencing
Protection
Figure 13 shows a typical application that requires overvoltage
VG
VS
VD
VG
VS
VD
and power supply sequencing protection. The application shows
a Hot-Insertion rack system. This involves plugging a circuit
board or module into a live rack via an edge connector. In this
T
R
P+
P-CHANNEL
P+
T
R
N+
N-CHANNEL
N+
T
R
E
E
E
N
N
N
C
H
N–
C
H
P–
C
H
type of application it is not possible to guarantee correct power
supply sequencing. Correct power supply sequencing means
that the power supplies should be connected before any external
signals. Incorrect power sequencing can cause a CMOS device
BURIED OXIDE LAYER
to “latch up.” This is true of most CMOS devices regardless of
SUBSTRATE (BACKGATE)
the functionality. RC networks are used on the supplies of the
channel protector (Figure 13) to ensure that the rest of the
Figure 12. Trench Isolation
circuitry is powered up before the channel protectors. In this
way, the outputs of the channel protectors are clamped well
APPLICATIONS INFORMATION
Overvoltage and Power Supply Sequencing Protection
The ADG466 and ADG467 are ideal for use in applications
where input overvoltage protection is required and correct
power supply sequencing cannot always be guaranteed. The
below VDD and VSS until the capacitors are charged. The diodes
ensure that the supplies on the channel protector never exceed
the supply rails of the board when it is being disconnected.
Again this ensures that signals on the inputs of the CMOS
devices never exceed the supplies.
overvoltage protection ensures that the output voltage of the
–6–
REV. 0
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