AD8600 データシートの表示（PDF） - Analog Devices
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AD8600 Datasheet PDF : 16 Pages
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AD8600
ELECTRICAL CHARACTERISTICS (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = –5 V, VREF = +3.500 V, –40°C ≤ TA ≤ +85°C,
unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
INTERFACE TIMING1, 2
Clock (EN) Frequency
fCLK
Data Loading
12.5
Clock (EN) High Pulse Width
tCH
40
Clock (EN) LowPulse Width
tCL
40
Data Setup Time
tDS
40
Data Hold Time
tDH
10
Address Setup Time
tAS
0
Address Hold Time
tAH
0
Valid Address to Data Valid
tAD
160
Load Enable Setup Time
Load Enable Hold Time
Read/Write to Clock (EN)
Read/Write to DataBus Hi-Z
Read/Write to DataBus Active
Clock (EN) to Read/Write
E Clock (EN) to Chip Select
Chip Select to Clock (EN)
Chip Select to Data Valid
T Chip Select to DataBus Hi-Z
Reset Pulse Width
tLS
tLH
tRWC
tRWZ
tRWD
tTWH
tTCH
tCSC
tCSD
tCSZ
tRS
NOTES
1Guaranteed by design not subject to production test.
E 2All logic input signals have maximum rise and fall times of 2 ns.
Specifications subject to change without notice.
L R/W
DATA
O ADDR
S EN
CS
tRWZ
tDS
tDH
tAS
tAH
tRWC
tCSC
tCH
tCL
tTWH
HIGH-Z
tTCH
0
0
30
0
0
30
25
R/W
tRWD
HIGH -Z
DATA
tAD
ADDR
EN
tCSD
CS
120
120
120
150
tCSZ
OB Figure 2. Write Timing
Figure 3. Readback Timing
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LD
tLS
tLH
EN
tRS
RS
OUT
tS1
tS1
Figure 4. Write to DAC Register & Voltage Output Settling
Timing (CS= High, Prevents Input Register Changes)
–4–
REV. 0
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