AD8600 データシートの表示（PDF） - Analog Devices

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AD8600

16-Channel, 8-Bit Multiplying DAC

Analog Devices 

AD8600

20

19

VCC = +5V

VEE = –5V

VREF = 3.5V

18

5

4

VCC = +5V

VEE = –5V

3

VREF = 3.5V

2

CODE = 00H

1

χ + 3σ

χ

0

χ − 3σ

17

–1

χ + 3σ

–2

16

χ

–3

χ − 3σ

–4

15

–75 –50 –25 0 25 50 75 100 125

–5

0 200 400 600 800 1000 1200

TEMPERATURE – °C

T = HOURS OF OPERATION AT +125°C

Figure 14. Supply Current vs. Temperature

Figure 15. Output Voltage Drift

Accelerated by Burn-In

Operation

E The AD8600 is a 16-channel voltage output, 8-bit digital to

analog converter. The AD8600 operates from a single +5 V

supply, or for a wider output swing range, the part can operate

T from dual supplies of ± 5 V or ±6 V or a single supply of +7 V.

The DACs are based upon a unique R-2R ladder structure*

that removes the possibility of current injection from the refer-

ence to ground during code switching. Each of the 8-bit DACs

E has an output amplifier to provide 16 low impedance outputs.

With a single external reference, 16 independent dc output lev-

els can be programmed through a parallel digital interface. The

interface includes 4 bits of address (A0–A3), 8 bits of data

L (DB0–DB7), a read/write select pin (R/W), an enable clock

strobe (EN), a DAC register load strobe (LD), and a chip select

pin (CS). Additionally a reset pin (RS) is provided to asynchro-

nously reset all 16 DACs to 0 V output.

O D/A Converter Section

The internal DAC is an 8-bit voltage mode device with an out-

put that swings from DACGND to the external reference volt-

age, VREF. The equivalent schematic of one of the DACs is

S shown in Figure 16. The DAC uses an R-2R ladder to ensure

accuracy and linearity over the full temperature range of the part.

The switches shown are actually N and P-channel MOSFETs to

allow maximum flexibility and range in the choice of reference

B VREF

R

R

O TO 15

VOUT

R

R

R

R

Amplifier Section

The output of the DAC ladder is buffered by a rail-to-rail out-

put amplifier. This amplifier is configured as a unity gain fol-

lower as shown in Figure 16. The input stage of the amplifier

contains a PNP differential pair to provide low offset drift and

noise. The output stage is shown in Figure 17. It employs

complementary bipolar transistors with their collectors con-

nected to the output to provide rail-to-rail operation. The NPN

transistor enters into saturation as the output approaches the

negative rail. Thus, in single supply, the output low voltage is

limited by the saturation voltage of the transistor. For the tran-

sistors used in the AD8600, this is approximately 40 mV. The

AD8600 was not designed to swing to the positive rail in con-

trast to some of ADI’s other DACs (for example, the AD8582).

The output stage of the amplifier is actually capable of swinging

to the positive rail, but the input stage limits this swing to ap-

proximately 1.0 V below VCC.

VCC

VOUT

VEE

DACs

R

Figure 17. Equivalent Analog Output Circuit

R

R

During normal operation, the output stage can typically source

and sink ± 1 mA of current. However, the actual short circuit

R

R

*R = 30kΩ

TYPICALLY

current is much higher. In fact, each DAC is capable of sourc-

ing 20 mA and sinking 8 mA during a short condition. The

DACGND

2R

absolute maximum ratings state that, at most, four DACs can

be shorted simultaneously. This restriction is due to current

densities in the metal traces. If the current density is too high,

Figure 16. Equivalent Schematic of Analog Channel

voltage drops in the traces will cause a loss in linearity perfor-

voltage. The switches’ low ON resistance and matching is im-

portant in maintaining the accuracy of the R-2R ladder.

mance for the other DACs in the package. Thus to ensure long-

term reliability, no more than four DACs should be shorted

simultaneously.

*Patent Pending.

–8–

REV. 0

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