ST16C580(2005) データシートの表示（PDF） - Exar Corporation

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ST16C580
(Rev.:2005)

UART WITH 16-BYTE FIFO’s AND INFRARED (IrDA) ENCODER/DECODER

Exar Corporation 

ST16C580

SYMBOL DESCRIPTION

Symbol

-IOR

-IOW

INT

-RXRDY

-TXRDY

-BAUDOUT

-DDIS

-OP1

-OP2

RCLK

Pin

Signal

48 type

Pin Description

19

I Read strobe (active low strobe). A logic 0 on this pin transfers

the contents of the 580 data bus to the CPU.

16

I Write strobe (active low strobe) - A logic 0 on this pin transfers

the contents of the CPU data bus to the addressed internal

register.

30

O Interrupt Request.

29

O Receive Ready. A logic 0 indicates receive data ready status,

i.e. the RHR is full or the FIFO has one or more RX characters

available for unloading. This pin goes to a logic 0 when the

FIFO/RHR is full or when there are more characters available

in either the FIFO or RHR.

23

O Transmit Ready. Buffer ready status is indicated by a logic

0, i.e., at least one location is empty and available in the

FIFO or THR. This pin goes to a logic 1 when there are no

more empty locations in the FIFO or THR.

12

O Baud Rate Generator Output. This pin provides the 16X clock

of the selected data rate from the baud rate generator. The

RCLK pin must be connected externally to -BAUDOUT when

the receiver is operating at the same data rate.

22

O Drive Disable. This pin goes to a logic 0 when the external

CPU is reading data from the 580. This signal can be used

to disable external transceivers or other logic functions.

34

O Output-1 (User Defined) - See bit-2 of modem control register

(MCR bit-2).

31

O Output-2 (User Defined). This pin provides the user a general

purpose output. See bit-3 modem control register (MCR bit-

3).

5

I Receive Clock Input. This pin is used as external 16X clock

input to the receiver section. External connection to -

Baudout pin is required in order to utilize the internal baud

rate generator.

Rev. 1.22

4

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