LTC1662CMS8 データシートの表示（PDF） - Linear Technology

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LTC1662CMS8

Ultralow Power, Dual 10-Bit DAC in MSOP

Linear Technology 

LTC1662

DEFI ITIO S

where VOUT is the output voltage of the DAC measured at

the given input code.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

LSB = VREF/1024

Resolution (n): Defines the number of DAC output states

(2n) that divide the full-scale range. Resolution does not

imply linearity.

Voltage Offset Error (VOS): Nominally, the voltage at the

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Figure 2).

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

WU

W

TI I G DIAGRA

SCK

SDI

CS/LD

t1

t2

t3

t4

t6

t9

t11

A3

A2

A1

X1

X0

t5

t7

1662 TD

U

OPERATIO

SCK

SDI

CS/LD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0

CONTROL CODE

(SCK ENABLED)

INPUT CODE

INPUT WORD W0

DON’T CARE

Figure 1. Register Loading Sequence

(INSTRUCTION

EXECUTED) 1662 F01

7

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