ADM8690(1997) データシートの表示（PDF） - Analog Devices
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ADM8690 Datasheet PDF : 16 Pages
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ADM8690–ADM8695
+APPLICATION INFORMATION
Increasing the Drive Current
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter-
nal transistor.
+5V INPUT
POWER
BATTERY
0.1µF
PNP TRANSISTOR
VCC
BATT
ON
VOUT
VBATT ADM8691
ADM8693
ADM8695
0.1µF
Figure 17. Increasing the Drive Current
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during power-
down if the resistor is connected to VCC.
+5V INPUT
POWER
0.1µF
RECHARGEABLE
BATTERY
I = VOUT – VBATT
R
R
VCC
VOUT
VBATT
ADM869x
0.1µF
Figure 18. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the PFO output and the PFI input as shown in Figure 19.
When PFO is low, resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, the series combina-
tion of R3 and R4 source current into the PFI summing junc-
tion. This results in differing trip levels for the comparator.
+7V TO +15V
INPUT
POWER
R1
+5V
7805
PFI
VCC
1.3V
PFO
R4
TO µP NMI
R2
ADM869x
R3
5V
PFO
0V
0V
VL
VH
VIN
( ) VH = 1.3V
1+ R1 + R1
R2 R3
( ) VL = 1.3V
1+ R1 – R1 (5V – 1.3V)
R2 1.3V (R3 + R4)
ASSUMING R4 < < R3 THEN
( ) HYSTERESIS VH – VL = 5V
R1
R2
Figure 19. Adding Hysteresis to the Power Fail Comparator
Monitoring the Status of the Battery
The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery volt-
age and generates an active low PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. This can be done under processor control using CEOUT.
Since CEOUT is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
+5V INPUT
POWER
BATTERY
20kΩ
OPTIONAL
TEST LOAD
VBATT
10MΩ
VCC
PFI ADM869x
10MΩ
CEOUT
PFO
LOW BATTERY
SIGNAL TO
µP I/O PIN
CEIN
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
Figure 20. Monitoring the Battery Status
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a three-state buffer (Figure
21a). When three-stated, the WDI input will float, thereby dis-
abling the watchdog timer.
WATCHDOG
STROBE
CONTROL
INPUT
WD I
ADM869x
Figure 21a. Programming the Watchdog Input
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously three-state the buffer. This
would then prevent the ADM869x from detecting that the mi-
croprocessor is no longer operating correctly. In most cases a
better method is to extend the watchdog period rather than dis-
abling the watchdog. This may be done under program control
using the circuit shown in Figure 21b. When the control input is
high, the OSC SEL pin is low and the watchdog timeout is set
by the external capacitor. A 0.01 µF capacitor sets a watchdog
timeout delay of 100 seconds. When the control input is low,
the OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which di-
ode in Figure 21b is used. With D1 inserted, the internal timeout is
set at 100 ms; with D2 inserted the timeout is set at 1.6 s.
CONTROL
INPUT*
D1
OSC SEL
D2
ADM869x
OSC IN
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Programming the Watchdog Input
–10–
REV. 0
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