AT43310 データシートの表示（PDF） - Atmel Corporation

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AT43310

USB Hub

Atmel Corporation 

Figure 1. Power Supply Connection

exists, AT43310 removes the power from that port by de-

activating the port’s PWRx# pin and reports the condition to

the Host.

Figure 1 shows an example of the power supply connection

for a typical AT43310 port.

Port [1:4] Power Control

Each port has signals for port power management and for

port status feedback (PWR[1:4], OVL[1:4], and STAT[1:4]).

The AT43310 monitors and switches the power to each

port individually.

PWR[1:4] are open drain outputs that control the power to

the downstream ports. The AT43310 asserts a low value to

ports PWR[1:4] to turn on the power to the port. During

power up, reset, and initialization of the Hub, PWR[1:4] is

in-active. PWR[1:4] is asserted when the Host instructs the

Hub to power the port through the SetPortPower = ON

command. Additionally PWR[1:4] is de-asserted by the Hub

when an overcurrent condition is detected at the port.

For proper operation of PWR[1:4], an external pull-up resis-

tor to VCC5 is required for PWR[1:4] pins. To control the

power to the port, any switch with a low voltage drop with

full power applied is acceptable. The AT43310 is designed

for a simple, low cost P-channel MOSFET to use as the

switch.

To detect a port overload, the AT43310 compares OVL[1:4]

to a common VREF defined by the designer.

OVL[1:4] should be attached to the power supply of the

respective downstream port. If OVL[1:4] drops below the

reference voltage VREF for more than 1 ms, the AT43310

treats the drop in voltage as a fault condition on the port’s

power supply. Upon this fault condition, the AT43310 sets

the port’s PORT_OVER_CURRENT status bit and the

port’s C_PORT_OVER_CURRENT bit. The AT43310 will

additionally shut off the power to the port by de-activating

the port’s PWR[1:4] signal.

The STAT[1:4] pins are not required by the USB specifica-

tion. STAT[1:4] provide feedback to the user whenever a

device is properly connected to the port. An LED and series

resistor connected to STAT[1:4] can be used to provide

visual feedback. The default state of STAT[1:4] is inactive.

After a port is enabled AT43310 will assert the port’s

STAT[1:4].

Oscillator and Phase-Locked-Loop

To reduce EMI and power dissipation in the system, the

AT43310 on-chip oscillator is designed to operate with a 6

MHz external crystal. An on-chip PLL generates the high

frequency for the clock/data separator of the Serial Inter-

face Engine. In the suspended state, the oscillator circuitry

is turned off.

A 6 MHz parallel resonance quartz crystal with a load

capacitance of approximately 10 pF is recommended. If the

crystal load capacitor is larger, external capacitors added to

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AT43310

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