5962-8862801YA データシートの表示（PDF） - Aeroflex UTMC
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5962-8862801YA
Aeroflex UTMC
5962-8862801YA Datasheet PDF : 61 Pages
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DMA SIGNALS
NAME
DMAR
LCC/FP
56
PIN NUMBER
PGA
A10
132 FP
70
DMAG
57
A9
72
DMAGO
67
B5
88
DMACK
58
B8
74
BURST
74
A1
98
TSCTL
55
B9
69
TYPE
TTO
TI
TO
TTO
TO
TO
ACTIVE
DESCRIPTION
ZL DMA Request. The BCRTM issues this
signal when access to RAM is required. It
goes inactive after receiving a DMAG
signal.
AL DMA Grant. This input to the BCRTM
allows the BCRT to access RAM. It is
recognized 45ns before the rising edge of
MCLKD2.
AL DMA Grant Out. If DMAG is received but
not needed, it passes through to this output.
ZL DMA Acknowledge. The BCRTM asserts
this signal to confirm receipt of DMAG, it
stays low until memory access is complete.
AH Burst (DMA Cycle). This indicates that the
current DMA cycle transfers at least two
words; worst case is five words plus a
“dummy” word.
AL Three-State Control. This signal indicates
when the BCRTM is actually accessing
memory. The host subsystem’s address and
data lines must be in the high-impedance
state when the signals active. This signal
assists in placing the external data and
address buffers into the high-impedance
state.
CLOCK SIGNALS
NAME
CLK
LCC/FP
21
PIN NUMBER
PGA
35
132 FP
18
TYPE
TI
MCLK
65
C5
85
TI
MCLKD2
71
A3
94
TO
POWER AND GROUND
NAME
VDD
PIN NUMBER
LCC/FP
PGA
132 FP
23, 43, 64, 84 L6, C9, C6, 17, 34, 50, 66,
’E3 83, 100, 115,
132
TYPE
PWR
ACTIVE
--
--
--
ACTIVE
--
DESCRIPTION
Clock. The 12MHz input clock requires a
50% ± 10% duty cycle with an accuracy
of ± 0.01%. The accuracy is required in
order to meet the Manchester encoding/
decoding requirements of MIL-STD-
1553B.
Memory Clock. This is the input clock
frequency the BCRT uses for memory
accesses. The memory cycle time is
equal to two MCLK cycles. Therefore,
RAM access time is dependent upon the
chosen MCLK frequency (6MHz mini-
mum, 12MHz maximum). Please see the
BCRT DMA timing diagrams in this
chapter.
Memory Clock Divided by Two. This
signal is the Memory Clock input
divided by two. It assists the host sub-
system in synchronizing DMA events.
DESCRIPTION
+5V
VSS 1, 22, 42, 63 F3, J6, F10, 1, 16, 33, 49, GND
B6
67, 82, 99, 116
--
Ground
BCRT-11
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