5962-8862801YA データシートの表示（PDF） - Aeroflex UTMC

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5962-8862801YA

UT1553B BCRT bus controller/remote terminal/monitor. Lead finish optional. Total dose none.

Aeroflex UTMC 

1.0 INTRODUCTION

The monolithic CMOS UT1553B BCRT provides the

system designer with an intelligent solution to

MIL-STD-1553B multiplexed serial data bus design

problems. The UT1553B BCRT is a single-chip device that

implements two of the defined MIL-STD-1553B functions

- Bus Controller and Remote Terminal. Designed to reduce

host CPU overhead, the BCRT’s powerful state machines

automatically execute message transfers, provide interrupts,

and generate status information. Multiple registers offer

many programmable functions as well as extensive

information for host use. In the BC mode, the BCRT uses a

linked-list message scheme to provide the host with

message chaining capability. The BCRT enhances memory

use by supporting variable-size, relocatable data blocks. In

the RT mode, the BCRT implements time-tagging and

message history functions. It also supports multiple (up to

128) message buffering and variable length messages to

any subaddress.

The UT1553B BCRT is an intelligent, versatile, and easy to

implement device -- a powerful asset to system designers.

1.1 Features - Remote Terminal (RT) Mode

Indexing

The BCRT is programmable to index or buffer messages on

a subaddress-by-subaddress basis. The BCRT, which can

index as many as 128 messages, can also assert an interrupt

when either the selected number of messages is reached or

every time a specified subaddress is accessed.

Variable Space Allocation

The BCRT can use as little or as much memory (up to 64K)

as needed.

Selectable Data Storage

Address programmability within the BCRT provides

flexible data placement and convenient access.

Sequential Data Storage

The BCRT stores/retrieves, by subaddress, all messages in

the order in which they are transacted.

Sequential Message Status Information

The BCRT provides message validity, time-tag, and word-

count information, and stores it sequentially in a separate,

cross-referenced list.

Illegalizing Mode Codes and Subaddresses

The host can declare mode codes and subaddresses illegal

by setting the appropriate bit(s) in memory.

Programmable Interrupt Selection

The host CPU can select various events to cause an interrupt

with provision for high and standard priority interrupts.

Interrupt History List

The BCRT provides an Interrupt History List that records,

in the order of occurrence, the events that caused the

interrupts. The list length is programmable.

1.2 Features - Bus Controller (BC) Mode

Multiple Message Processing

The BCRT autonomously processes any number of

messages or lists of messages that may be stored in a 64K

memory space.

Automatic Intermessage Delay

When programmed by the host, the BCRT can delay a

host-specified time before executing the next message

in sequence.

Automatic Polling

When polling, the BCRT interrogates the remote terminals

and then compares their status word responses to the

contents of the Polling Compare

Register. The BCRT can interrupt the host CPU if an

erroneous remote terminal status word response occurs.

Automatic Retry

The BCRT can automatically retry a message on busy,

message error, and/or response time-out conditions. The

BCRT can retry up to four times on the same or on the

alternate bus.

Programmable Interrupt Selection

The host CPU can select various events to cause an interrupt

with provision for high and standard priority interrupts.

Interrupt History List

The BCRT provides an Interrupt History List that records,

in the order of occurrence, the events that caused the

interrupts. The list length is program- mable.

Variable Space Allocation

The BCRT uses as little or as much memory (up to 64K)

as needed.

Selectable Data Storage

Address programmability within the BCRT provides

flexible data placement and convenient access.

BCRT-3

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