LA3401 データシートの表示（PDF） - SANYO -> Panasonic
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LA3401 Datasheet PDF : 15 Pages
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LA3401
Decorder circuit (Refer to the Block Diagram in the Sample Application Circuit.)
The LA3401 adopts a decoder circuit of chopper type. The sub signal syncdetected by this decoder is applied to the post
amplifier minus input through Rb as shown in the Sample Application Circuit. This signal is matrixed with the main
signal coming out of amplifier A5 and passing through RC.
The gain for the sub signal is :
VS
R1 ·
Rb
2
π
or VS
R2 ·
Rb
2
π
The gain for the main signal is :
VM
VR1
Ra + VR1
·
R1
Rc
or
VM
VR1
Ra + VR1
·
R2
Rc
R1, R2 : Post amplifier feedback resistor
VS : Peak value of input sub signal
VR1 : Semifixed resistor for separation adjust
VM : Peak value of input main signal
In the LA3401, the gain of the main signal is varied with VR1 to adjust the separation. Since the IF output is generally
such that the sub signal level is lower than the main signal level, the separation can be adjusted by attenuating the main
signal level with VR1. The use of an antibirdie filter across the IF output and the FM input of the LA3401 may cause the
sub signal level to be raised, and when the sub signal level is higher than the main signal level the separation cannot be
adjusted with VR1. In this case, the sub signal level is attenuated to be less than the main signal level and applied to the
LA3401 and the separation is adjusted with VR1.
No.1868–11/15
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