SAA7111 データシートの表示（PDF） - Philips Electronics
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SAA7111 Datasheet PDF : 64 Pages
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Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
7 PINNING
SYMBOL
TRST
TCK
RTCO
IICSA
SDA
SCL
n.c.
n.c.
n.c.
n.c.
TDO
TDI
TMS
VSSA2
AI22
VDDA2
AI21
VSSA1
AI12
VDDA1
AI11
VSSS
AOUT
VDDA0
VSSA0
VREF
VDD5
VSS5
LLC
LLC2
CREF
PINS
PLCC68 QFP64
1
58
2
59
3
60
4
61
5
62
6
63
7
64
8
−
9
−
10
1
11
2
12
3
13
4
14
5
15
6
16
7
17
8
18
9
19
10
20
11
21
12
22
13
23
14
24
15
25
16
26
17
27
18
28
19
29
20
30
21
31
22
I/O
DESCRIPTION
I
I
O
I
I/O
I/O
−
−
−
−
O
I
I
GND
I
P
I
GND
I
P
I
GND
O
P
GND
O
P
GND
O
O
O
Test reset input not (active LOW), for boundary scan test;
notes 1, 2, 3 and 4.
Test clock input for boundary scan test; note 3.
Real time control output: contains information about actual system
clock frequency, subcarrier frequency and phase and PAL sequence.
I2C-bus slave address select input; 0 → 48H for write, 49H for read,
1 → 4AH for write, 4BH for read.
I2C-bus serial data input/output.
I2C-bus serial clock input/output.
Not connected.
Not connected.
Not connected.
Not connected.
Test data output for boundary scan test; note 3.
Test data input for boundary scan test; note 3.
Test mode select input for boundary scan test or scan test; note 3.
Ground for analog supply voltage channel 2.
Analog input 22.
Positive supply voltage (+5 V) for analog channel 2.
Analog input 21.
Ground for analog supply voltage channel 1.
Analog input 12.
Positive supply voltage (+5 V) for analog channel 1.
Analog input 11.
Substrate (connected to analog ground).
Analog test output; for testing the analog input channels.
Positive supply voltage (+5 V) for internal CGC.
Ground for internal CGC.
Vertical reference output signal (I2C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).
Positive digital supply voltage 5 (+5 V).
Digital ground for positive supply voltage 5.
Line-locked system clock output (27 MHz).
Line-locked clock 1⁄2 output (13.5 MHz).
Clock reference output: this is a clock qualifier signal distributed by
the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualifier) is provided on this pin.
1998 May 15
6
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