VPX3224E データシートの表示（PDF） - Micronas

部品番号

コンポーネント説明

メーカー

VPX3224E

Video Pixel Decoders

Micronas 

ADVANCE INFORMATION

Contents, continued

Page

Section Title

27

2.10.

Operational Modes

27

2.10.1.

Open Mode

27

2.10.2.

Scan Mode

29

2.11.

Windowing the Video Field

30

2.12.

Temporal Decimation

31

2.13.

Data Slicer

31

2.13.1.

Slicer Features

31

2.13.2.

Data Broadcast Systems

32

2.13.3.

Slicer Functions

32

2.13.3.1. Input

32

2.13.3.2. Automatic Adaptation

32

2.13.3.3. Standard Selection

32

2.13.3.4. Output

34

2.14.

VBI Data Acquisition

34

2.14.1.

Raw VBI Data

35

2.14.2.

Sliced VBI Data

36

2.15.

Control Interface

36

2.15.1.

Overview

36

2.15.2.

I2C-Bus Interface

36

2.15.3.

Reset and I2C Device Address Selection

36

2.15.4.

Protocol Description

37

2.15.5.

FP Control and Status Registers

38

2.16.

Initialization of the VPX

38

2.16.1.

Power-on-Reset

38

2.16.2.

Software Reset

38

2.16.3.

Low Power Mode

39

2.17.

JTAG Boundary-Scan, Test Access Port (TAP)

39

2.17.1.

General Description

39

2.17.2.

TAP Architecture

39

2.17.2.1. TAP Controller

39

2.17.2.2. Instruction Register

39

2.17.2.3. Boundary Scan Register

40

2.17.2.4. Bypass Register

40

2.17.2.5. Device Identification Register

40

2.17.2.6. Master Mode Data Register

40

2.17.3.

Exception to IEEE 1149.1

40

2.17.4.

IEEE 1149.1–1990 Spec Adherence

40

2.17.4.1. Instruction Register

40

2.17.4.2. Public Instructions

41

2.17.4.3. Self-Test Operation

41

2.17.4.4. Test Data Registers

41

2.17.4.5. Boundary-Scan Register

41

2.17.4.6. Device Identification Register

41

2.17.4.7. Performance

45

2.18.

Enable/Disable of Output Signals

Micronas

VPX 322xE

3

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