AD636JCHIP データシートの表示（PDF） - Analog Devices
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AD636JCHIP Datasheet PDF : 8 Pages
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AD636
100
100
0.01%
10
0.1%
ERROR
10
1.0
10%
1%
ERROR
ERROR
1.0
VALUES FOR CAV AND ERROR
1% SETTLING TIME FOR
0.1 STATED % OF READING
0.1
AVERAGING ERROR*
ACCURACY ؎20% DUE TO
COMPONENT TOLERANCE
*% dc ERROR + % RIPPLE (PEAK)
0.01
1
10
100
1k
0.01
10k
100k
INPUT FREQUENCY – Hz
Figure 5. Error/Settling Time Graph for Use with the
Standard rms Connection
The primary disadvantage in using a large CAV to remove ripple
is that the settling time for a step change in input level is in-
creased proportionately. Figure 5 shows the relationship be-
tween CAV and 1% settling time is 115 milliseconds for each
microfarad of CAV. The settling time is twice as great for de-
creasing signals as for increasing signals (the values in Figure 5
are for decreasing signals). Settling time also increases for low
signal levels, as shown in Figure 6.
VIN
1
ABSOLUTE
14
VALUE
2 AD636
13
–VS
3
+– 4
CAV
5
SQUARER
12
DIVIDER
11
CURRENT
MIRROR
10
6
+
9
10k⍀
7
B– UF
8
10k⍀
+VS
(FOR SINGLE POLE, SHORT Rx,
REMOVE C3)
+
C2 –
Rx
10k⍀
–
C3 +
Vrms OUT
Figure 7. 2 Pole ‘’Post’’ Filter
10
p-p RIPPLE
(ONE POLE)
CAV = 1F
C2 = 4.7F
p-p RIPPLE
CAV = 1F (FIG 1)
1
DC ERROR
CAV = 1F
(ALL FILTERS)
p-p RIPPLE
(TWO POLE)
10.0
CAV = 1F, C2 = C3 = 4.7F
0.1
10
100
1k
10k
7.5
FREQUENCY – Hz
Figure 8. Performance Features of Various Filter Types
5.0
RMS MEASUREMENTS
AD636 PRINCIPLE OF OPERATION
2.5
The AD636 embodies an implicit solution of the rms equation
1.0
0
1mV
10mV
100mV
1V
rms INPUT LEVEL
Figure 6. Settling Time vs. Input Level
A better method for reducing output ripple is the use of a
“post-filter.” Figure 7 shows a suggested circuit. If a single pole
filter is used (C3 removed, RX shorted), and C2 is approxi-
mately 5 times the value of CAV, the ripple is reduced as shown
in Figure 8, and settling time is increased. For example, with
CAV = 1 µF and C2 = 4.7 µF, the ripple for a 60 Hz input is re-
duced from 10% of reading to approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. The values of CAV and C2 can therefore be reduced
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole post-filter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The values
of CAV, C2, and C3 can then be reduced to allow extremely fast
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of CAV, since the dc error is
dependent upon this value and is independent of the post filter.
For a more detailed explanation of these topics refer to the
RMS-to-DC Conversion Application Guide, 2nd Edition, available
that overcomes the dynamic range as well as other limitations
inherent in a straightforward computation of rms. The actual
computation performed by the AD636 follows the equation:
V
rms
=
Avg. VVIrNm2s
Figure 9 is a simplified schematic of the AD636; it is subdivided
into four major sections: absolute value circuit (active rectifier),
squarer/divider, current mirror, and buffer amplifier. The input
voltage, VIN, which can be ac or dc, is converted to a unipolar
current I1, by the active rectifier A1, A2. I1 drives one input of
the squarer/divider, which has the transfer function:
I4 =
I12
I3
The output current, I4, of the squarer/divider drives the current
mirror through a low-pass filter formed by R1 and the externally
connected capacitor, CAV. If the R1, CAV time constant is much
greater than the longest period of the input signal, then I4 is
effectively averaged. The current mirror returns a current I3,
which equals Avg. [I4], back to the squarer/divider to complete
the implicit rms computation. Thus:
I4
=
Avg.
I12
I4
=
I1
rms
from Analog Devices.
REV. B
–5–
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