AN5192K データシートの表示（PDF） - Panasonic Corporation

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AN5192K

Single chip IC with I2C bus Interface for PAL/NTSC color TV system

Panasonic Corporation 

ICs for TV

AN5192K

s Electrical Characteristics at Ta = 25°C (continued)

Parameter

Symbol

Conditions

Min Typ Max Unit

Synchronizing signal processing circuit

Horizontal free-running oscillation frequency

Horizontal output pulse duty cycle

Horizontal pull-in range

PAL vertical free-running oscillation

frequency

fHO

τHO

fHP

fVO-P

Without sync. signal input

15.33 15.63 15.93 kHz

Upward going pulse duty cycle

31 37 43 %

Difference from fH = 15.625 kHz ±500 ±650  Hz

Data 0E − D2 = 1, D3 = 0

48 50 52 Hz

Forced 50 Hz mode, no sync. signal input

NTSC vertical free-running oscillation fVO-N Data 0E − D2 = 1, D3 = 1

58 60 62 Hz

frequency

Forced 60 Hz mode, no sync. signal input

Vertical output pulse width

PAL vertical pull-in range

NTSC vertical pull-in range

Horizontal output voltage (high)

Horizontal output voltage (low)

Vertical output voltage (high)

Vertical output voltage (low)

Picture center variable range

τVO For both PAL/NTSC

9 10 11 1/fH

fVP-P fH = 15.625 kHz, forced 50 Hz mode 46  54 Hz

fVP-N fH = 15.75 kHz, forced 60 Hz mode

56  64 Hz

V56H High level DC voltage

3.2 3.5 3.8 V

V56L Low level DC voltage

0  0.3 V

V58H High level DC voltage

3.9 4.2 4.5 V

V58L Low level DC voltage

0  0.3 V

∆THC Change amount of phase difference 2.6 3.2 4.4 µS

between H Sync. and H-out of

Data 0A = 80 to 8F

Overvoltage protective operation voltage VXRAY Pin 55 minimum voltage at which 0.60 0.68 0.76 V

H-out stops to appear

Vertical frequency discrimination (50)

f50 Vertical frequency to become V57 47  55 Hz

= Low (< 0.5 V)

Vertical frequency discrimination (60)

f60 Vertical frequency to become V57 57  63 Hz

= High (> 4.5 V)

Sync. signal clamp voltage (Ver.)

V45 Clamp voltage of V45

1.0 1.3 1.6 V

Sync. signal clamp voltage (Hor.) V46 Clamp voltage of V46

1.0 1.3 1.6 V

Horizontal output start voltage

VfHS Minimum V50 to become f0 > 10 kHz, 3.4 4.2 5.0 V

when horizontal oscillation output

is 1 V[p-p] or more.

I2C interface

Sink current when ACK

IACK Maximum value of pin 21 sink

current at ACK

2.0 2.5 5.0 mA

SCL, SDA signal input high level VIHI

3.1  5.0 V

SCL, SDA signal input low level VILO

Maximum frequency allowable to input fImax

0

100 

0.9 V

 Kbit/s

9

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