AD9912 データシートの表示（PDF） - Analog Devices

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AD9912

1 GSPS Direct Digital Synthesizer with 14-Bit DAC

Analog Devices 

REVISION HISTORY

6/10—Rev. E to Rev. F

Changed Default Value of Register 0x003 to 0x19 (Table 12).....31

5/10—Rev. D to Rev. E

Deleted 64-Lead LFCSP (CP-64-1).................................. Universal

Changes to SYSCLK PLL Enabled/ Maximum Input Rate of System

Clock PFD, Table 2 ...............................................................................6

Updated Outline Dimensions........................................................39

Changes to Ordering Guide...........................................................39

11/09—Rev. C to Rev. D

Added 64-Lead LFCSP (CP-64-7).................................... Universal

Changes to Serial Port Timing Specifications and

Propagation Delay Parameters ........................................................6

Added Exposed Paddle Notation to Figure 2 ................................8

Changes to Power Supply Partitioning Section...........................25

Change to Serial Control Port Section .........................................26

Changes to Figure 52 ......................................................................28

Added Exposed Paddle Notation to Outline Dimensions.........38

Changes to Ordering Guide...........................................................39

AD9912

7/09—Rev. B to Rev. C

Changes to Logic Outputs Parameter, Table 1 .............................. 3

Changes to AVDD (Pin 25, Pin 26, Pin 29, and Pin 30) ............25

6/09—Rev. A to Rev. B

Changes to Figure 40 and Direct Digital Synthesizer Section ..17

Changes to Figure 48 ......................................................................22

Changes to Table 11 ........................................................................30

Changes to Table 22 and Table 23.................................................34

1/08—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Table 4 ............................................................................ 8

Changes to Typical Performance Characteristics .......................10

Changes to Functional Description Section................................19

Changes to Single-Ended CMOS Output Section ......................21

Changes to Harmonic Spur Reduction Section ..........................21

Changes to Power Supply Partitioning Section...........................25

10/07—Revision 0: Initial Version

Rev. F | Page 3 of 40

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