D16550 データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

メーカー

D16550

Configurable UART with FIFO

Unspecified 

DLL or DLM to prevent long counts on initial

load.

Modem Control Logic controls the interface

with the MODEM or data set (or a peripheral

device emulating a MODEM).

Interrupt Controller - D16550 consists fully

prioritized interrupt system controller. It

controls interrupt requests to the CPU and

interrupt priority. Interrupt controller contains

Interrupt Enable (IER) and Interrupt

Identification (IIR) registers.

Receiver Control - Receiving starts when the

falling edge on Serial Input (SI) during IDLE

State is detected. After starting the SI input is

sampled every 16 internal baud cycles as it is

shown in figure below. When the logic 1 state

is detected during START bit it means that the

False Start bit was detected and receiver back

to the IDLE state.

Receiver FIFO - The Rx FIFO is 16 levels

deep, it receives data until the number of

bytes in the FIFO equals the selected interrupt

trigger level. At that time if Rx interrupts are

enabled, the UART will issue an interrupt to

the CPU. The Rx FIFO will continue to store

bytes until it holds 16 of them. It will not

accept any more data when it is full. Any more

data entering the Rx shift register will set the

Overrun Error flag.

Transmitter Control module controls

transmission of written to THR (Transmitter

Holding register) character via serial output

SO. The new transmission starts on the next

overflow signal of internal baud generator,

after writing to THR register or Transmitter

FIFO. Transmission control contains THR

register and transmitter shift register.

Transmitter FIFO - the Tx portion of the

UART transmits data through SO as soon as

the CPU loads a byte into the Tx FIFO. The

UART will prevent loads to the Tx FIFO if it

currently holds 16 characters. Loading to the

Tx FIFO will again be enabled as soon as the

next character is transferred to the Tx shift

register. These capabilities account for the

largely autonomous operation of the Tx. The

UART starts the above operations typically

with a Tx interrupt.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the ACTEL®

devices after Place & Route (all key features

have been included):

Device

Speed

grade

TILES

FUSION1

-2

1109

ProASIC31

-2

1109

ProASIC3e1 -2

1109

IGLOO1

STD

1109

IGLOO+1

STD

1109

IGLOOe1

STD

1135

1- FIFOs implemented in RAM’s – 304 Bits

Fmax

93 MHz

96 MHz

94 MHz

65 MHz

63 MHz

49 MHz

Core performance in ACTEL® devices

CONTACT

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: iinnffoo@@ddccdd..ppll

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Distributors:

Please check hhtttpp::///wwwwww..ddccdd..ppll//aappaarrttnn..pphhpp

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.

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