82801HB データシートの表示（PDF） - Unspecified

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82801HB

Intel® I/O Controller Hub 8 (ICH8) Family

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5.6

5.7

5.8

5.9

5.10

5.5.5 Software Commands............................................................................. 132

LPC DMA ........................................................................................................ 132

5.6.1 Asserting DMA Requests........................................................................ 132

5.6.2 Abandoning DMA Requests .................................................................... 133

5.6.3 General Flow of DMA Transfers............................................................... 133

5.6.4 Terminal Count .................................................................................... 133

5.6.5 Verify Mode ......................................................................................... 134

5.6.6 DMA Request Deassertion...................................................................... 134

5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 135

8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming .............................................................................. 136

5.7.2 Reading from the Interval Timer............................................................. 137

5.7.2.1 Simple Read........................................................................... 137

5.7.2.2 Counter Latch Command.......................................................... 137

5.7.2.3 Read Back Command .............................................................. 138

8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 139

5.8.1 Interrupt Handling ................................................................................ 140

5.8.1.1 Generating Interrupts.............................................................. 140

5.8.1.2 Acknowledging Interrupts ........................................................ 140

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 141

5.8.2 Initialization Command Words (ICWx) ..................................................... 141

5.8.2.1 ICW1 .................................................................................... 141

5.8.2.2 ICW2 .................................................................................... 142

5.8.2.3 ICW3 .................................................................................... 142

5.8.2.4 ICW4 .................................................................................... 142

5.8.3 Operation Command Words (OCW) ......................................................... 142

5.8.4 Modes of Operation .............................................................................. 143

5.8.4.1 Fully Nested Mode................................................................... 143

5.8.4.2 Special Fully-Nested Mode........................................................ 143

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 143

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 143

5.8.4.5 Poll Mode ............................................................................... 144

5.8.4.6 Cascade Mode ........................................................................ 144

5.8.4.7 Edge and Level Triggered Mode ................................................ 144

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 144

5.8.4.9 Normal End of Interrupt........................................................... 144

5.8.4.10 Automatic End of Interrupt Mode .............................................. 145

5.8.5 Masking Interrupts ............................................................................... 145

5.8.5.1 Masking on an Individual Interrupt Request ................................ 145

5.8.5.2 Special Mask Mode .................................................................. 145

5.8.6 Steering PCI Interrupts ......................................................................... 145

Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.9.1 Interrupt Handling ................................................................................ 146

5.9.2 Interrupt Mapping ................................................................................ 146

5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 147

5.9.4 Front Side Bus Interrupt Delivery ........................................................... 147

5.9.4.1 Edge-Triggered Operation ........................................................ 148

5.9.4.2 Level-Triggered Operation........................................................ 148

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 148

5.9.4.4 Interrupt Message Format........................................................ 148

Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame ......................................................................................... 149

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150

5.10.5 Data Frame Format .............................................................................. 151

Intel® ICH8 Family Datasheet

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