82801HB データシートの表示（PDF） - Unspecified
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82801HB Datasheet PDF : 890 Pages
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5.14
5.15
5.16
5.13.10ALT Access Mode.................................................................................. 177
5.13.10.1Write Only Registers with Read Paths in ALT
Access Mode .......................................................................... 177
5.13.10.2PIC Reserved Bits ................................................................... 179
5.13.10.3Read Only Registers with Write Paths in ALT
Access Mode .......................................................................... 180
5.13.11System Power Supplies, Planes, and Signals ............................................ 180
5.13.11.1Power Plane Control with SLP_S3#, SLP_S4#,
SLP_S5# and SLP_M# ............................................................. 180
5.13.11.2SLP_S4# and Suspend-To-RAM Sequencing ............................... 181
5.13.11.3PWROK Signal ........................................................................ 181
5.13.11.4CPUPWRGD Signal .................................................................. 181
5.13.11.5VRMPWRGD Signal .................................................................. 181
5.13.11.6BATLOW# (Battery Low) (Mobile Only) ...................................... 182
5.13.11.7Controlling Leakage and Power Consumption
during Low-Power States ......................................................... 182
5.13.12Clock Generators.................................................................................. 182
5.13.12.1Clock Control Signals from Intel® ICH8 to Clock
Synthesizer (Mobile Only) ........................................................ 183
5.13.13Legacy Power Management Theory of Operation ....................................... 183
5.13.13.1APM Power Management (Desktop Only) .................................... 183
5.13.13.2Mobile APM Power Management (Mobile Only) ............................ 183
System Management (D31:F0).......................................................................... 184
5.14.1 Theory of Operation.............................................................................. 184
5.14.1.1 Detecting a System Lockup ...................................................... 184
5.14.1.2 Handling an Intruder ............................................................... 184
5.14.1.3 Detecting Improper Firmware Hub Programming ......................... 185
5.14.2 TCO Modes .......................................................................................... 185
5.14.2.1 TCO Legacy/Compatible Mode .................................................. 185
5.14.2.2 Advanced TCO Mode ............................................................... 187
5.14.2.3 Advanced TCO BMC Mode ........................................................ 187
IDE Controller (D31:F1) (Mobile Only)................................................................ 189
5.15.1 PIO Transfers ...................................................................................... 189
5.15.1.1 PIO IDE Timing Modes ............................................................. 189
5.15.1.2 IORDY Masking....................................................................... 190
5.15.1.3 PIO 32-Bit IDE Data Port Accesses ............................................ 190
5.15.1.4 PIO IDE Data Port Prefetching and Posting ................................. 190
5.15.2 Bus Master Function ............................................................................. 191
5.15.2.1 Physical Region Descriptor Format ............................................ 191
5.15.2.2 Bus Master IDE Timings ........................................................... 192
5.15.2.3 Interrupts .............................................................................. 192
5.15.2.4 Bus Master IDE Operation ........................................................ 192
5.15.2.5 Error Conditions...................................................................... 193
5.15.3 Ultra ATA/100/66/33 Protocol ................................................................ 194
5.15.3.1 Operation .............................................................................. 194
5.15.4 Ultra ATA/33/66/100 Timing .................................................................. 195
5.15.5 ATA Swap Bay ..................................................................................... 195
5.15.6 SMI Trapping ....................................................................................... 195
SATA Host Controller (D31:F2, F5) .................................................................... 196
5.16.1 Theory of Operation.............................................................................. 197
5.16.1.1 Standard ATA Emulation .......................................................... 197
5.16.1.2 48-Bit LBA Operation............................................................... 197
5.16.2 SATA Swap Bay Support ....................................................................... 198
5.16.3 Intel® Matrix Storage Technology Configuration (Intel® ICH8R,
ICH8DH, ICH8DO, and ICH8M-E Only) .................................................... 198
5.16.3.1 Intel® Matrix Storage Manager RAID Option ROM........................ 199
5.16.4 Power Management Operation................................................................ 199
Intel® ICH8 Family Datasheet
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