82801HB データシートの表示（PDF） - Unspecified
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コンポーネント説明
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82801HB Datasheet PDF : 890 Pages
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5.20
5.21
5.22
5.23
5.24
5.25
5.26
5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 219
5.19.10USB 2.0 Based Debug Port .................................................................... 220
5.19.10.1 Theory of Operation ............................................................... 220
SMBus Controller (D31:F3) ............................................................................... 225
5.20.1 Host Controller..................................................................................... 225
5.20.1.1 Command Protocols ................................................................ 226
5.20.2 Bus Arbitration..................................................................................... 229
5.20.3 Bus Timing .......................................................................................... 230
5.20.3.1 Clock Stretching ..................................................................... 230
5.20.3.2 Bus Time Out (Intel® ICH8 as SMBus Master)............................. 230
5.20.4 Interrupts / SMI#................................................................................. 230
5.20.5 SMBALERT# ........................................................................................ 232
5.20.6 SMBus CRC Generation and Checking...................................................... 232
5.20.7 SMBus Slave Interface .......................................................................... 232
5.20.7.1 Format of Slave Write Cycle ..................................................... 233
5.20.7.2 Format of Read Command........................................................ 235
5.20.7.3 Format of Host Notify Command ............................................... 237
Intel® High Definition Audio Overview ................................................................ 238
5.21.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 238
5.21.1.1 Dock Sequence....................................................................... 238
5.21.1.2 Exiting D3/CRST# when Docked ............................................... 239
5.21.1.3 Cold Boot/Resume from S3 When Docked .................................. 240
5.21.1.4 Undock Sequence ................................................................... 240
5.21.1.5 Interaction Between Dock/Undock and Power
Management States ................................................................ 241
5.21.1.6 Relationship between HDA_DOCK_RST# and HDA_RST# ............. 241
Intel® Active Management Technology (Intel® AMT)
(Intel® ICH8DO and ICH8M-E Only)) ................................................................. 242
5.22.1 Intel® AMT Features ............................................................................. 242
5.22.2 Intel® AMT Requirements ...................................................................... 242
Serial Peripheral Interface (SPI) ........................................................................ 243
5.23.1 SPI Supported Feature Overview ............................................................ 243
5.23.1.1 Flash Descriptor...................................................................... 244
5.23.1.2 Flash Access .......................................................................... 245
5.23.1.3 Program Register Software Sequencing...................................... 245
5.23.1.4 Direct Access Security ............................................................. 245
5.23.1.5 Register Access Security .......................................................... 245
5.23.2 SPI Device Compatibility Requirements ................................................... 246
5.23.2.1 Device Requirements for System BIOS Storage Only ................... 246
5.23.2.2 Device Requirements for Intel® AMT, ASF and AFSC
Firmware ............................................................................... 246
5.23.2.3 Device Requirements for GbE ................................................... 247
5.23.3 Serial Flash Command Set ..................................................................... 247
5.23.3.1 Required Command Set for Interoperability ................................ 247
5.23.3.2 Recommended Command Set and Opcodes ................................ 248
5.23.3.3 JEDEC Device Identification ...................................................... 248
5.23.3.4 Multiple Page Write Usage Model............................................... 248
Intel® Quiet System Technology (Desktop Only) ................................................. 249
5.24.1 PWM Outputs....................................................................................... 249
5.24.2 TACH Inputs ........................................................................................ 249
Thermal Sensors ............................................................................................. 249
Intel® Quick Resume Technology (Intel® ICH8DH Only) ....................................... 250
5.26.1 5.26.1 Visual Off .................................................................................. 250
5.26.2 5.26.2 CE-like On/Off ........................................................................... 250
5.26.3 Intel® Quick Resume Technology Signals................................................. 250
5.26.4 Power Button Sequence ........................................................................ 251
Intel® ICH8 Family Datasheet
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