NQ6311 データシートの表示（PDF） - Unspecified
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NQ6311 Datasheet PDF : 902 Pages
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5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.2.4 Hot-Plug ........................................................................................... 127
PCI-to-PCI Bridge (D30:F0)............................................................................... 129
5.3.1 PCI Bus Interface ............................................................................... 129
5.3.2 PCI Bridge as an Initiator .................................................................... 129
5.3.3 Parity Error Detection and Generation ................................................... 131
5.3.4 PCIRST#........................................................................................... 132
5.3.5 PCI-to-PCI Bridge Model ..................................................................... 132
5.3.6 IDSEL to Device Number Mapping ........................................................ 132
5.3.7 Standard PCI Bus Configuration Mechanism ........................................... 132
Integrated LAN Controller and SERDES/Kumeran Interface.................................... 133
5.4.1 Integrated LAN Controller ................................................................... 133
5.4.2 Packet Reception and Transmission ...................................................... 135
5.4.3 Buffer and Descriptor Structure............................................................ 135
5.4.4 LAN Controller PCI Express* Bus Interface ............................................ 135
5.4.5 Wake-Up .......................................................................................... 140
5.4.6 CSMA/CD Unit ................................................................................... 144
5.4.7 802.1q VLAN Support ......................................................................... 145
5.4.8 EEPROM Interface .............................................................................. 146
5.4.9 Serial Flash Interface.......................................................................... 146
5.4.10 Intel® 631xESB/632xESB I/O Controller Hub MAC-PHY Interconnection..... 148
5.4.11 LAN Disabling .................................................................................... 149
Board Management Controller (BMC).................................................................. 151
5.5.1 Management Microcontroller System Theory of Operation ........................ 151
5.5.2 Feature List....................................................................................... 151
5.5.3 Memory Sub-System .......................................................................... 152
5.5.4 Instruction Cache and Data Cache........................................................ 153
5.5.5 External Interfaces............................................................................. 153
5.5.6 Memory Host DMA ............................................................................. 160
5.5.7 Cryptography Module ......................................................................... 161
LPC Bridge (with System and Management Functions) (D31:F0)............................. 162
5.6.1 LPC Interface .................................................................................... 162
DMA Operation (D31:F0) .................................................................................. 166
5.7.1 Channel Priority ................................................................................. 167
5.7.2 Address Compatibility Mode................................................................. 168
5.7.3 Summary of DMA Transfer Sizes .......................................................... 168
5.7.4 Autoinitialize ..................................................................................... 169
5.7.5 Software Commands .......................................................................... 170
LPC DMA ........................................................................................................ 170
5.8.1 Asserting DMA Requests ..................................................................... 170
5.8.2 Abandoning DMA Requests .................................................................. 171
5.8.3 General Flow of DMA Transfers ............................................................ 171
5.8.4 Terminal Count .................................................................................. 172
5.8.5 Verify Mode....................................................................................... 172
5.8.6 DMA Request De-Assertion .................................................................. 172
5.8.7 SYNC Field / LDRQ# Rules .................................................................. 173
8254 Timers (D31:F0) ...................................................................................... 174
5.9.1 Timer Programming............................................................................ 174
5.9.2 Reading from the Interval Timer .......................................................... 175
8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 176
5.10.1 Interrupt Handling ............................................................................. 177
5.10.2 Initialization Command Words (ICWx) .................................................. 179
5.10.3 Operation Command Words (OCW)....................................................... 180
5.10.4 Modes of Operation ............................................................................ 180
5.10.5 Masking Interrupts ............................................................................. 182
5.10.6 Steering PCI Interrupts ....................................................................... 183
Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 183
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Intel® 631xESB/632xESB I/O Controller Hub Datasheet
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