NQ6311 データシートの表示（PDF） - Unspecified
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NQ6311 Datasheet PDF : 902 Pages
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5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.11.1 Interrupt Handling ............................................................................. 183
5.11.2 Interrupt Mapping.............................................................................. 183
5.11.3 PCI/PCI Express* Message-Based Interrupts ......................................... 184
5.11.4 System Bus Interrupt Delivery ............................................................ 185
Serial Interrupt (D31:F0) ................................................................................. 187
5.12.1 Start Frame ...................................................................................... 187
5.12.2 Data Frames ..................................................................................... 187
5.12.3 Stop Frame....................................................................................... 188
5.12.4 Specific Interrupts Not Supported by way of SERIRQ .............................. 188
5.12.5 Data Frame Format............................................................................ 188
Real Time Clock (D31:F0)................................................................................. 189
5.13.1 Update Cycles ................................................................................... 190
5.13.2 Interrupts......................................................................................... 190
5.13.3 Lockable RAM Ranges ........................................................................ 190
5.13.4 Century Rollover ............................................................................... 190
5.13.5 Clearing Battery-Backed RTC RAM ....................................................... 191
Processor Interface (D31:F0) ............................................................................ 192
5.14.1 Processor Interface Signals ................................................................. 192
5.14.2 Dual-Processor Issues ........................................................................ 195
Power Management (D31:F0) ........................................................................... 195
5.15.1 Features........................................................................................... 195
5.15.2 Intel® 631xESB/632xESB I/O Controller Hub and System Power States .... 196
5.15.3 System Power Planes ......................................................................... 198
5.15.4 SMI#/SCI Generation......................................................................... 198
5.15.5 Dynamic Processor Clock Control ......................................................... 200
5.15.6 Sleep States ..................................................................................... 201
5.15.7 Thermal Management ........................................................................ 204
5.15.8 Event Input Signals and Their Usage .................................................... 205
5.15.9 ALT Access Mode ............................................................................... 208
5.15.10 System Power Supplies, Planes, and Signals.......................................... 211
5.15.11 Clock Generators ............................................................................... 213
5.15.12 Legacy Power Management Theory of Operation .................................... 213
System Management (D31:F0).......................................................................... 213
5.16.1 Theory of Operation ........................................................................... 214
5.16.2 Heartbeat and Event Reporting by way of SMBUS .................................. 217
IDE Controller (D31:F1) ................................................................................... 221
5.17.1 PIO Transfers.................................................................................... 221
5.17.2 Bus Master Function........................................................................... 223
5.17.3 Ultra ATA/100/66/33 Protocol ............................................................. 226
5.17.4 Ultra ATA/33/66/100 Timing ............................................................... 227
5.17.5 IDE Swap Bay ................................................................................... 227
5.17.6 SMI Trapping .................................................................................... 228
SATA Host Controller (D31:F2).......................................................................... 228
5.18.1 Legacy Operation .............................................................................. 228
5.18.2 AHCI Operation ................................................................................. 231
High-Precision Event Timers ............................................................................. 235
5.19.1 Timer Accuracy ................................................................................. 236
5.19.2 Interrupt Mapping.............................................................................. 236
5.19.3 Periodic Versus Non-Periodic Modes ..................................................... 236
5.19.4 Enabling the Timers ........................................................................... 237
5.19.5 Interrupt Levels ................................................................................ 237
5.19.6 Handling Interrupts............................................................................ 237
5.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors ........................... 238
USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................ 238
5.20.1 Data Structures in Main Memory .......................................................... 238
5.20.2 Data Transfers to/from Main Memory ................................................... 238
Intel® 631xESB/632xESB I/O Controller Hub Datasheet
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