ADM1062ACPZ-REEL7 データシートの表示（PDF） - Analog Devices
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ADM1062ACPZ-REEL7 Datasheet PDF : 35 Pages
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Data Sheet
ADM1062
Parameter
IOL3
ISINK3
RPULL-UP
ISOURCE (VPx)3
Min Typ
16 20
Three-State Output Leakage Current
Oscillator Frequency
90 100
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Input High Current, IIH
−1
Input Low Current, IIL
Input Capacitance
5
Programmable Pull-Down Current, IPULL-DOWN
20
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Output Low Voltage, VOL3
SERIAL BUS TIMING4
Clock Frequency, fSCLK
Bus Free Time, tBUF
1.3
Start Setup Time, tSU;STA
0.6
Stop Setup Time, tSU;STO
0.6
Start Hold Time, tHD;STA
0.6
SCL Low Time, tLOW
1.3
SCL High Time, tHIGH
0.6
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
100
Data Hold Time, tHD;DAT
5
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
10
Max Unit
20 mA
60 mA
29 kΩ
2
mA
10 μA
110 kHz
V
0.8 V
μA
1
μA
pF
μA
V
0.8 V
0.4 V
400 kHz
μs
μs
μs
μs
μs
μs
300 ns
300 ns
ns
ns
1
μA
μs
Test Conditions/Comments
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
VPDO = 14.4 V
All on-chip time delays derived from this clock
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0 V
VDDCAP = 4.75 V TA = 25°C if known logic state is required
IOUT = −3.0 mA
VIN = 0 V
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3 Specification is not production tested but is supported by characterization data at initial product release.
4 Timing specifications are guaranteed by design and supported by characterization data.
Rev. D | Page 7 of 35
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