AD7927 データシートの表示（PDF） - Unspecified
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コンポーネント説明
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AD7927 Datasheet PDF : 20 Pages
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AD7927
ADD2
0
0
0
0
1
1
1
1
Table II. Channel Selection
ADD1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
Analog Input Channel
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Table III. Power Mode Selection
PM1 PM0 Mode
1 1 Normal Operation. In this mode, the AD7927 remains in full power mode, regardless of the status of any of the logic
inputs. This mode allows the fastest possible throughput rate from the AD7927.
1 0 Full Shutdown. In this mode, the AD7927 is in full shutdown mode with all circuitry on the AD7927 powering down.
The AD7927 retains the information in the Control Register while in full shutdown. The part remains in full shutdown
until these bits are changed.
0 1 Auto Shutdown. In this mode, the AD7927 automatically enters full shutdown mode at the end of each conversion
when the Control Register is updated. Wake-up time from full shutdown is 1 ms and the user should ensure that 1 ms
has elapsed before attempting to perform a valid conversion on the part in this mode.
0 0 Invalid Selection. This configuration is not allowed.
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the
Control Register allows the user to select a particular mode of
operation of the sequencer function. Table IV outlines the four
modes of operation of the sequencer.
Table IV. Sequence Selection
SEQ SHADOW Sequence Type
00
This configuration means that the sequence function is not used. The analog input channel selected for each
individual conversion is determined by the contents of the channel address bits ADD0 through ADD2 in each
prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without
the sequencer function being used, where each write to the AD7927 selects the next channel for conversion. (See
Figure 2.)
01
This configuration selects the Shadow Register for programming. The following write operation will load the
contents of the Shadow Register. This will program the sequence of channels to be converted on continuously with
each successive valid CS falling edge. (See Shadow Register, Table V, and Figure 3.) The channels selected need
not be consecutive.
10
If the SEQ and SHADOW bits are set in this way, the sequence function will not be interrupted upon completion
of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while
in a sequence, without terminating the cycle.
11
This configuration is used in conjunction with the channel address bits ADD2 to ADD0 to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the
channel address bits in the Control Register. (See Figure 4.)
–10–
REV. 0
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