AD7927 データシートの表示（PDF） - Unspecified

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AD7927

8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP

Unspecified 

AD7927

PIN CONFIGURATION

20-Lead TSSOP

SCLK 1

20 AGND

DIN 2

19 VDRIVE

CS 3 AD7927 18 DOUT

AGND 4 TOP VIEW 17 AGND

AVDD 5 (Not to Scale) 16 VIN0

AVDD 6

15 VIN1

REFIN 7

14 VIN2

AGND 8

13 VIN3

VIN7 9

12 VIN4

VIN6 10

11 VIN5

Pin No.

1

Mnemonic

SCLK

2

DIN

3

CS

4, 8, 17, 20 AGND

5, 6

7

16–9

AVDD

REFIN

VIN0–VIN7

18

DOUT

19

VDRIVE

PIN FUNCTION DESCRIPTIONS

Function

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock

input is also used as the clock source for the AD7927s conversion process.

Data In. Logic input. Data to be written to the AD7927s Control Register is provided on this input

and is clocked into the register on the falling edge of SCLK (see the Control Register section).

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7927 and framing the serial data transfer.

Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input

signals and any external reference signal should be referred to this AGND voltage. All AGND pins

should be connected together.

Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the

0 V to 2 ¥ REFIN range, AVDD should be from 4.75 V to 5.25 V.

Reference Input for the AD7927. An external reference must be applied to this input. The voltage

range for the external reference is 2.5 V ± 1% for specified performance.

Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed

into the on-chip track-and-hold. The analog input channel to be converted is selected by using the

address bits ADD2 through ADD0 of the Control Register. The address bits in conjunction with the

SEQ and SHADOW bits allow the sequencer to be programmed. The input range for all input channels

can extend from 0 V to REFIN or 0 V to 2 ¥ REFIN, as selected via the RANGE bit in the Control Register.

Any unused input channels should be connected to AGND to avoid noise pickup.

Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the

AD7927 consists of two leading zeros, two address bits indicating which channel the conversion result

corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be

selected as straight binary or twos complement via the CODING bit in the Control Register.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface

of the AD7927 will operate.

–6–

REV. 0

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