BJ8P508/153
OTP ROM
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
︰
2F
R PAGE registers
R0
R1 (TCC)
R2 (PC)
R3 (Status)
R4 (RSR)
R5 (Port5)
R6 (Port6)
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Res
RF (Interrupt Status)
IOC PAGE registers
Reserve
CONT (Control Register
Reserve
Reserve
Reserve
IOC5 (I/O Port Control Register)
IOC6 (I/O Port Control Register)
Reserve
Reserve
Reserve
IOCB
Reserve
(Pull-down Registe
IOCC (Open-drain Contro
IOCD (Pull-high Control Registe
IOCF (Interrupt Mask Registe
General Registers
Fig. 4 Data memory configuration
This specification is subject to change without prior notice.
10
6.17.2007 (V2.0)