TOP252 データシートの表示（PDF） - Power Integrations, Inc
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TOP252 Datasheet PDF : 50 Pages
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TOP252-262
Pin Functional Description
DRAIN (D) Pin:
High-voltage power MOSFET DRAIN pin. The internal start-up
bias current is drawn from this pin through a switched high-
voltage current source. Internal current limit sense point for
drain current.
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package):
Input pin for external current limit adjustment and remote
ON/OFF. A connection to SOURCE pin disables all functions on
this pin.
E Package (eSIP-7C)
Y Package (TO-220-7C)
Note: Y package for TOP259-261
Exposed Pad
(Hidden)
Internally
Connected to
SOURCE Pin
VOLTAGE MONITOR (V) Pin (Y & M package only):
Input for OV, UV, line feed forward with DCMAX reduction, output
overvoltage protection (OVP), remote ON/OFF and device reset.
A connection to the SOURCE pin disables all functions on this pin.
MULTI-FUNCTION (M) Pin (P & G packages only):
This pin combines the functions of the VOLTAGE MONITOR (V)
and EXTERNAL CURRENT LIMIT (X) pins of the Y package into
one pin. Input pin for OV, UV, line feed forward with DCMAX
+
DC
Input
Voltage
-
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IOV)
RLS
4 MΩ For RLS = 4 MΩ
VUV = 102.8 VDC
VOV = 451 VDC
DCMAX@100 VDC = 76%
D
V
DCMAX@375 VDC = 41%
CONTROL
C
S
X
For RIL = 12 kΩ
ILIMIT = 61%
RIL
12 kΩ
See Figure 55b for
other resistor values
(RIL) to select different
ILIMIT values.
Figure 5. TOP254-258 Y and All M/E/L Package Line Sense and Externally Set
Current Limit.
12345 7
VXCFS D
L Package (eSIP-7F)
Tab Internally
Connected to
SOURCE Pin
12345 7
VXCFS D
12345 7
VXCSG D
Lead Bend
Outward from Drawing
(Refer to eSIP-7F Package
Outline Drawing)
M Package
V1
10 S
Y Package (TO-220-7C)
Note: Y package for TOP254-258
X2
C3
9S
8S
7S
D5
6S
P and G Package
Tab Internally
Connected to
SOURCE Pin
M1
8S
C2
7S
D4
6S
5S
12345 7
VXCSF D
PI-4644-091108
Figure 4. Pin Configuration (Top View).
+
DC
Input
Voltage
-
VUV = IUV × RLS + VV (IV = IUV)
VOV = IOV × RLS + VV (IV = IOV)
RLS
4 MΩ For RLS = 4 MΩ
VUV = 102.8 VDC
VOV = 451 VDC
DCMAX@100 VDC = 76%
D
V
DCMAX@375 VDC = 41%
CONTROL
C
For RIL = 12 kΩ
S
XG
ILIMIT = 61%
RIL
12 kΩ
See Figure 55b for
other resistor values
(RIL) to select different
ILIMIT values.
Figure 6. TOP259-261 Y Package Line Sense and External Current Limit.
+
DC
Input
Voltage
VUV = IUV × RLS + VM (IM = IUV)
VOV = IOV × RLS + VM (IM = IOV)
RLS
4
MΩ
For RLS = 4 MΩ
VUV = 102.8
VDC
VOV = 451 VDC
DCMAX@100 VDC = 76%
DCMAX@375 VDC = 41%
D
M
CONTROL
C
-
S
Figure 7. P/G Package Line Sense.
PI-4712-120307
6
Rev. H 06/13
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