HV9910 データシートの表示（PDF） - Supertex Inc
部品番号
コンポーネント説明
メーカー
HV9910 Datasheet PDF : 11 Pages
| |||
HV9910
Ordering Information
SO-16
HV9910NG
Package Options
DIP-8
HV9910P
SO-8
HV9910LG
Absolute Maximum Ratings
VIN to GND ...................................….........................-0.5V to +470V
CS.....................…………………………………...-0.3V to Vdd + 0.3V
LD, PWM_D to GND...........……........…............-0.3V to (Vdd --0.3V)
GATE to GND .................................………......-0.3V to (Vdd + 0.3V)
VDDMAX…………………………………………………………..……13.5V
Continuous Power Dissipation (TA = +25°C) (Note 1)
16-Pin SO (derate 7.5mW/°C above +25°C).…...…….….....750mW
8-Pin DIP (derate 9mW/°C above +25°C)…..……..…….......900mW
8-Pin SO (derate 6.3mW/°C above +25°C)…..……..…….....630mW
Operating Temperature Range ...................……......-40°C to +85°C
Junction Temperature....................................……….............+125°C
Storage Temperature Range .......................……...-65°C to +150°C
Stresses beyond those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Specifications (TA = 25°C unless noted otherwise)
Symbol Description
Min
VINDC
Input DC supply voltage range
8.0
IINsd
Shut-Down mode supply current
VDD
Internally regulated voltage
7.0
VDDmax
IDD(ext)
UVLO
∆UVLO
VEN(lo)
VEN(hi)
REN
VCS(hi)
VGATE(hi)
VGATE(lo)
fOSC
Maximal pin Vdd voltage
VDD current available for external circuitry 1
VDD undervoltage lockout threshold
VDD undervoltage lockout hysteresis
Pin PWM_D input low voltage
Pin PWM_D input high voltage
Pin PWM_D pull-down resistance
Current sense pull-in threshold voltage
GATE high output voltage
GATE low output voltage
Oscillator frequency
6.45
2.4
50
225
VDD-0.3
0
20
80
DMAXhf Maximum Oscillator PWM Duty Cycle
VLD
Linear Dimming pin voltage range
0
TBLANK Current sense blanking interval
150
tDELAY Delay from CS trip to GATE lo
tRISE
GATE output rise time
tFALL
GATE output fall time
1 Also limited by package power dissipation limit, whichever is lower.
Typ
0.5
7.5
6.7
500
100
250
25
100
215
30
30
Max
450
1
8.0
13.5
1.0
6.95
1.0
150
275
VDD
0.3
30
120
100
250
280
300
50
50
Units
V
mA
V
V
mA
V
mV
V
V
kΩ
mV
V
V
kHz
kHz
%
mV
ns
ns
ns
ns
Conditions
DC input voltage
Pin PWM_D to GND, VIN = 8V
VIN = 8–450V, IDD(ext)=0, pin Gate
open
When an external voltage applied
to pin Vdd
VIN = 8–100V
Vin rising
Vin falling
VIN = 8–450V
VIN = 8–450V
VEN = 5V
@TA = -40°C to +85°C
IOUT = 10mA
IOUT = -10mA
ROSC = 1.00MΩ
ROSC = 226kΩ
FPWMhf = 25kHz, at GATE, CS to
GND. GBD
@TA = <85°C, Vin = 12V
VCS = 0.55VLD, VLD = VDD
Vin = 12V, VLD = 0.15, VCS = 0 to
0.22V after TBLANK
CGATE = 500pF
CGATE = 500pF
2
C110504
Share Link: 