Si3056
Si3018/19/10
Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Cycle time, SCLK
tc
244
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—
50
—
%
Delay Time, SCLK↑ to FSYNC↓
td1
—
—
20
ns
Delay Time, SCLK↑ to SDO Valid
td2
—
—
20
ns
Delay Time, SCLK↑ to FSYNC↑
td3
—
—
20
ns
Setup Time, SDI Before SCLK ↓
tsu
25
—
—
ns
Hold Time, SDI After SCLK ↓
th
20
—
—
ns
Setup Time, FC↑ Before SCLK↑
tsfc
40
—
—
ns
Hold time, FC↑ After SCLK↑
thfc
40
—
—
ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
SCLK
FSYNC
(mode 0)
FSYNC
(mode 1)
16-Bit
SDO
16-Bit
SDI
FC
tc
td1
VOH
VOL
td3
td3
td2
D15
D14
tsu
th
D15
D14
D1
DD00
D1
D0
tsfc
thfc
Figure 3. Serial Interface Timing Diagram (DCE = 0)
Rev. 1.05
11