XC6SLX25-3 データシートの表示（PDF） - Unspecified
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XC6SLX25-3 Datasheet PDF : 10 Pages
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Spartan-6 Family Overview
Spartan-6 FPGA Device-Package Combinations and Available I/Os
Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in Table 2.
Due to the transceivers, the LX and LXT pinouts are not compatible.
Table 2: Spartan-6 Device-Package Combinations and Maximum Available I/Os
Package CPG196(1) TQG144(1) CSG225(2) FT(G)256(3) CSG324
FG(G)484(3,4) CSG484(4) FG(G)676(3) FG(G)900(3)
Size (mm)
8x8
20 x 20
13 x 13
17 x 17
15 x 15
23 x 23
19 x 19
27 x 27
31 x 31
Pitch (mm)
0.5
0.5
0.8
1.0
0.8
1.0
0.8
1.0
1.0
Device
User I/O
User I/O
User I/O
User I/O
GTPs
User
I/O
GTPs
User
I/O
GTPs
User
I/O
GTPs
User
I/O
GTPs
User
I/O
XC6SLX4
106
102
132
XC6SLX9
106
102
160
186
NA 200
XC6SLX16
106
160
186
NA 232
XC6SLX25
186
NA 226 NA 266
XC6SLX45
NA 218 NA 316 NA 320 NA 358
XC6SLX75
NA 280 NA 328 NA 408
XC6SLX100
NA 326 NA 338 NA 480
XC6SLX150
NA 338 NA 338 NA 498 NA 576
XC6SLX25T
2
190
2
250
XC6SLX45T
4
190
4
296
4 296
XC6SLX75T
4
268
4 292 8 348
XC6SLX100T
4
296
4 296 8 376 8 498
XC6SLX150T
4
296
4 296 8 396 8 540
Notes:
1. There is no memory controller on the devices in these packages.
2. Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the
XC6SLX4.
3. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
4. These packages support two of the four memory controllers in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and
XC6SLX150T devices.
Configuration
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits
is between 2.6 Mb and 33 Mb depending on device size but independent of the specific user-design implementation, unless
compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.
This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for
loading configuration are available.
Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations,
master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and
16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an
external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan
protocols to load bit-serial configuration data.
DS160 (v1.4) March 3, 2010
www.xilinx.com
Advance Product Specification
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