XC6SLX150-4 データシートの表示（PDF） - Unspecified

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XC6SLX150-4

Spartan-6 Family Overview

Unspecified 

Spartan-6 Family Overview

Spartan-6 FPGA Ordering Information

The Spartan-6 FPGA ordering information shown in Figure 1 applies to all packages, including Pb-Free.

X-Ref Target - Figure 1

Example: XC6SLX100T-2FGG676C

Device Type

Speed Grade

(-L1(1), -2, -3, -4(2))

Note:

1) -L1 is the ordering code for the lower power version.

Not all devices are offered in this version (LX only).

See the Spartan-6 FPGA data sheet for more information.

2) -4 speed grades are not available in all devices (LXT only).

Temperature Range:

C = Commercial (Tj = 0°C to +85°C)

I = Industrial (Tj = –40°C to +100°C)

Number of Pins

Pb-Free

Package Type

DS160_01_022410

Figure 1: Spartan-6 FPGA Ordering Information

Revision History

The following table shows the revision history for this document:

Date

02/02/09

05/05/09

06/24/09

11/05/09

03/03/10

Version

1.0

1.1

1.2

1.3

1.4

Description of Revisions

Initial Xilinx release.

Updated and simplified Designed for low cost, Multi-voltage, multi-standard SelectIO™ interface

banks, and Integrated Memory Controller blocks sections on page 1. Clarified PCI support on page 1is

only for the 33 MHz specification. Revised number of logic cells, slices, and maximum user I/O, and

added number of flip-flops to Table 1. In Table 2, revised user I/O counts, removed the XC6SLX25 in

the CSG225 package and the XC6SLX45T in the FGG676 package, added XC6SLX9 in the FT(G)256

package and XC6SLX45 in the CSG324 package, and added notes. Clerical edits to the following

sections: Dynamic Reconfiguration Port, Readback, CLBs, Slices, and LUTs, Frequency Synthesis,

PLLs, Programmable Data Width, and Memory Controller Block. Clarified I/O pin range, VREF banks,

and electrical characteristics in the Input/Output section.

Updated device/package combinations in Table 1 and Table 2 including adding the XC6SLX75 and

XC6SLX75T devices. Added ordering information and FPGA documentation sections. Removed

partial reconfiguration discussion from the Readback section.

Updated Figure 1, page 9 to show -4 speed grade. Added 64-bit PCI support on page 1. Updated User

I/O numbers in Table 1and Table 2. Clarifying edits to these sections: Configuration, Digital Signal

Processing—DSP48A1 Slice, Input/Output, and PCI Express documentation.

Updated the slice counts for the LX25 and LX25T in Table 1. Revised the Dynamic Reconfiguration

Port section. Added to the Spread-Spectrum Clocking section. Changed the PLL VCO maximum

frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition

of the -4 speed specification. Clarified configurations in the Programmable Data Width section.

Updated Low-Power Gigabit Transceiver operating rate.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND

CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED

WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE

SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE

PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES

THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

DS160 (v1.4) March 3, 2010

www.xilinx.com

Advance Product Specification

9

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