DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ADUM1280 データシートの表示(PDF) - Analog Devices

部品番号
コンポーネント説明
メーカー
ADUM1280 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Data Sheet
ADuM1280/ADuM1281/ADuM1285/ADuM1286
Table 6. For All Models
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Symbol Min
VIH
0.7 VDDx
VIL
VOH
VDDx − 0.1
VDDx − 0.4
VOL
Input Current per Channel
II
−10
Supply Current per Channel
Quiescent Input Supply Current IDDI(Q)
Quiescent Output Supply Current IDDO(Q)
Dynamic Input Supply Current IDDI(D)
Dynamic Output Supply Current IDDO(D)
Undervoltage Lockout
Positive VDDx Threshold
VDDxUV+
Negative VDDx Threshold
VDDxUV−
VDDX Hysteresis
VDDxUVH
AC SPECIFICATIONS
Output Rise/Fall Time
tR/tF
Common-Mode Transient Immunity1 |CM|
25
Refresh Period
tr
Typ
3.0
2.8
0.0
0.2
+0.01
0.4
1.2
0.08
0.015
2.6
2.4
0.2
3
35
1.6
Max
0.3 VDDx
0.1
0.4
+10
0.6
1.7
Unit
Test Conditions
V
V
V
IOx = −20 μA, VIx = VIxH
V
IOx = −4 mA, VIx = VIxH
V
IOx = 20 μA, VIx = VIxL
V
IOx = 4 mA, VIx = VIxL
μA
0 V ≤ VIx ≤ VDDx
mA
mA
mA/Mbps
mA/Mbps
V
V
V
ns
kV/μs
μs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining Vo > 0.8 VDDX. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OPERATION (A, B, AND C GRADES)
All typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire recommended
operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ 125°C, unless otherwise noted. Switching specifications are tested
with CL = 15 pF and CMOS signal levels unless otherwise noted.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Symbol
PW
tPHL, tPLH
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
PWD
tPSK
Channel Matching1
Codirectional
Opposing-Direction
Jitter
tPSKCD
tPSKOD
A Grade
Min Typ Max
1000
1
50
10
7
38
5
10
2
B Grade
Min Typ Max
40
25
35
3
3
16
3
6
2
C Grade
Min Typ Max
10
100
13 20 26
2
1.5
12
2
5
1
Unit
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
Test Conditions
Within PWD limit
Within PWD limit
50% input to 50%
output
|tPLH − tPHL|
Between any
two units at same
operating conditions
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-direction channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides
of the isolation barrier.
Rev. C | Page 5 of 22

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]