K9F2G08U0B データシートの表示（PDF） - Samsung
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K9F2G08U0B Datasheet PDF : 41 Pages
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K9F2G08B0B
K9F2G08U0B
Preliminary
FLASH MEMORY
Figure 1. K9F2G08X0B Functional Block Diagram
VCC
VSS
A12 - A28
X-Buffers
Latches
& Decoders
2,048M + 64M Bit
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
(2,048 + 64)Byte x 131,072
Data Register & S/A
Y-Gating
Command
Command
Register
CE
Control Logic
RE
& High Voltage
WE
Generator
CLE ALE WP
I/O Buffers & Latches
VCC
VSS
Global Buffers
Output
Driver
I/0 0
I/0 7
Figure 2. K9F2G08X0B Array Organization
1 Block = 64 Pages
(128K + 4k) Byte
128K Pages
(=2,048 Blocks)
2K Bytes
64 Bytes
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2,048 Blocks
= 2,112 Mbits
8 bit
Page Register
2K Bytes
I/O 0 ~ I/O 7
64 Bytes
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8
A9
A10
A11
*L
*L
*L
3rd Cycle A12
A13
A14
A15
A16
A17
A18
4th Cycle A20
A21
A22
A23
A24
A25
A26
5th Cycle A28
*L
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
I/O 7
A7
*L
A19
A27
*L
Column Address
Column Address
Row Address
Row Address
Row Address
Samsung Confidential
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