K9F2G08B0B-P データシートの表示（PDF） - Samsung
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K9F2G08B0B-P Datasheet PDF : 41 Pages
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K9F2G08B0B
K9F2G08U0B
Preliminary
FLASH MEMORY
VALID BLOCK
Parameter
K9F2G08X0B
Symbol
NVB
Min
2,008
Typ.
-
Max
2,048
Unit
Blocks
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
AC TEST CONDITION
(K9F2G08X0B-XCB0 :TA=0 to 70°C, K9F2G08X0B-XIB0:TA=-40 to 85°C,
K9F2G08B0B: Vcc=2.5V~2.9V, K9F2G08U0B: Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2G08X0B
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
Test Condition
Min
CI/O
VIL=0V
-
CIN
VIN=0V
-
Max
10
10
Unit
pF
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
H
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
H
X
X
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Command Input
Read Mode
Address Input(5clock)
Command Input
Write Mode
Address Input(5clock)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Samsung Confidential
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